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X5643 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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X5643 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 19 page  FN8135 Rev 1.00 Page 1 of 19 July 18, 2005 FN8135 Rev 1.00 July 18, 2005 X5643, X5645 (Replaces X25643, X25645) CPU Supervisor with 64Kbit SPI EEPROM DATASHEET FEATURES • Selectable watchdog timer •Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Determine watchdog or low voltage reset with a volatile flag bit • Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read • 64Kbits of EEPROM • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock™ protection —In circuit programmable ROM mode • 2MHz SPI interface modes (0,0 & 1,1) • Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • 2.7V to 5.5V and 4.5V to 5.5V power supply operation • Available packages —8-lead PDIP, 14-lead SOIC DESCRIPTION These devices combine four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers sys- tem cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be repro- grammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Reset & Watchdog Timebase Power-on and Generation VTRIP + - RESET/RESET Reset Low Voltage Status Register Protect Logic 16Kbits 16Kbits 32Kbits Watchdog Transition Detector WP VCC Threshold Reset logic X5643 = RESET X5645 = RESET |
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