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ISL6551IBZ Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # ISL6551IBZ
Description  ZVS Full Bridge PWM Controller
PDF  27 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6551IBZ Datasheet(HTML) 14 Page - Renesas Technology Corp

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FN9066 Rev 7.00
Page 14 of 27
Oct 28, 2015
ISL6551
• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent false
triggering, the leading edge of the sensed current signal is
blanked out by a period that can be programmed with the
R_LEB resistor. Internal switches gate the analog input to the
PWM comparator, implementing the blanking function that
eliminates response degrading delays, which would be
caused if filtering of the current feedback was incorporated.
The current ramp is blanked out during the resonant delay
period because no switching occurs in the lower FETs. The
leading edge blanking function will not be activated until the
soft-start (CSS) reaches over 400mV, as illustrated in
Figures 7 and 12. The leading edge blanking (LEB) function
can be disabled by tying the R_LEB pin to VDD, i.e., LEB = 1.
Never leave the pin floating.
- The blanking time can be estimated with Equation 9, whose
relationship can be seen in Figure 11. The percentages in
the figure are the tolerances at the two endpoints of the
curve.
(EQ. 9)
tLEB = 2 x R_LEB / kΩ + 15 (ns)
FIGURE 11. R_LEB vs tLEB
+20%
-18%
+51%
-11%
300
250
200
150
100
50
0
20
40
60
80
100
120
140
R_LEB (KΩ)
ADD RAMP
399k
BGREF
VDD
BLANK
0.1µ
R_RA
R_RA
ISENSE
200mV
+
-
RESDLY
LEB
SSL
ADJ_RAMP
RAMP_OUT
(TO PWM
COMPARATOR)
200mV
0
RAMP_OUT
200mV
ADJ_RAMP
ISENSE
RESDLY
LEB
SSL
RAMP_OUT
0X
X
BLANK
X0
0
BLANK
11
X
NO BLANK
1X
1
NO BLANK
FIGURE 12. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
SET
BLANKING
TIME
R_LEB
R_LEB
See Figure 7



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