ISL97673

FN7633 Rev.3.00

Page 23 of 28

Sep 19, 2017

The Vsc bits allow users to set 3 levels of channel

short-circuit thresholds or disable it.

The bit assignment is shown in Figure 34. The default

value for Register 0x08 is 0x1F.

Output Channel Select and Fault Readout

Register (0x09)

This register can be read or write; the bit position

corresponds to the channel. For example, Bit 0

corresponds to CH0 and Bit 4 corresponds to CH4 and so

on. Writing data to this register, it enables the channels

of interest. When reading data from this register, any

disabled channel and any faulted out channel will read as

0. This allows the user to determine which channel is

faulty and optionally not enabling it in order to allow the

rest of the system to continue to function. Additionally, a

faulted out channel can be disabled and re-enabled in

order to allow a retry for any faulty channel without

having to power-down the other channels.

The bit assignment is shown in Figure 35. The default for

Register 0x09 is 0x3F.

REGISTER 0x08

CONFIGURATION REGISTER

RESERVED DIRECT PWM PWM-TO-DC BSTSLEWRATE1 BSTSLEWRATE0

FSW

VSC1

VSC0

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

DirectPWM

Forces the PWMI signal to directly control the current sources. Note that there is some

synchronous delay between PWMI and current sources.

PWM-to-DC

Switches current sources on and varies DC level rather than PWMing.

BstSlewRate[1:0]

Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,

10 -75% drive strength, 11 to 100% drive strength.

FSW

2 levels of Switching Frequencies (0 = 1,200kHz, 1 = 600kHz)

VSC[1..0]

3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V)

FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER

FIGURE 35. DESCRIPTIONS OF OUTPUT CHANNEL REGISTER

REGISTER 0x09

OUTPUT CHANNEL REGISTER

Reserved Reserved

CH5

CH4

CH3

CH2

CH1

CH0

Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

CH[5..0]

CH5 = Channel 5, CH4 = Channel 4 and

so on