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PowerPC 603 RISC Microprocessor Technical Summary

1.2 Block Diagram

Figure 1 provides a block diagram of the 603 that illustrates how the execution units—IU, FPU, BPU, LSU,

and SRU—operate independently and in parallel.

The 603 provides address translation and protection facilities, including an ITLB, DTLB, and instruction

and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. Translation of

addresses for cache or external memory accesses are handled by the MMUs. Both units are discussed in

more detail in Sections 1.3, “Instruction Unit,” and 1.5.1, “Memory Management Units (MMUs).”

1.3 Instruction Unit

As shown in Figure 1, the 603 instruction unit, which contains a fetch unit, instruction queue, dispatch unit,

and BPU, provides centralized control of instruction flow to the execution units. The instruction unit

determines the address of the next instruction to be fetched based on information from the sequential fetcher

and from the BPU.

The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU

extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional

branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while

a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or

conditional branches unaffected by instructions in progress in the execution pipeline.

Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,

preserving the programming model of sequential execution. If any of these instructions are to be executed

in the BPU, they are decoded but not issued. Instructions to be executed by the FPU, IU, LSU, and SRU are

issued and allowed to complete up to the register write-back stage. Write-back is allowed when a correctly

predicted branch is resolved, and instruction execution continues without interruption along the predicted

path.

If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions

are issued from the correct path.

Freescale Semiconductor, Inc.

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