PowerPC 603 RISC Microprocessor Technical Summary

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PowerPC virtual environment architecture (VEA)—Describes the memory model for a

multiprocessor environment, defines cache control instructions, and describes other aspects of

virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may

not necessarily adhere to the OEA.

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PowerPC operating environment architecture (OEA)—Defines the memory management model,

supervisor-level registers, synchronization requirements, and the exception model.

Implementations that conform to the OEA also adhere to the UISA and the VEA.

The PowerPC architecture allows a wide range of designs for such features as cache and system interface

implementations.

Part 3 PowerPC 603 Microprocessor: Implementation

The PowerPC architecture is derived from the IBM POWER Architecture™ (Performance Optimized with

Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture

optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction

execution and is scalable to take advantage of future technological gains.

This section describes the PowerPC architecture in general, and specific details about the implementation

of the 603 as a low-power, 32-bit member of the PowerPC processor family.

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Features—Section 3.1, “Features,” describes general features that the 603 shares with the PowerPC

microprocessor family.

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Registers and programming model—Section 3.2, “PowerPC Registers and Programming Model,”

describes the registers for the operating environment architecture common among PowerPC

processors and describes the programming model. It also describes the additional registers that are

unique to the 603.

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Instruction set and addressing modes—Section 3.3, “Instruction Set and Addressing Modes,”

describes the PowerPC instruction set and addressing modes for the PowerPC operating

environment architecture, and defines and describes the PowerPC instructions implemented in the

603.

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Cache implementation—Section 3.4, “Cache Implementation,” describes the cache model that is

defined generally for PowerPC processors by the virtual environment architecture. It also provides

specific details about the 603 cache implementation.

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Exception model—Section 3.5, “Exception Model,” describes the exception model of the PowerPC

operating environment architecture and the differences in the 603 exception model.

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Memory management—Section 3.6, “Memory Management,” describes generally the conventions

for memory management among the PowerPC processors. This section also describes the 603’s

implementation of the 32-bit PowerPC memory management specification.

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Instruction timing—Section 3.7, “Instruction Timing,” provides a general description of the

instruction timing provided by the superscalar, parallel execution supported by the PowerPC

architecture and the 603.

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System interface—Section 3.8, “System Interface,” describes the signals implemented on the 603.

3.1 Features

The 603 is a high-performance, superscalar PowerPC microprocessor. The PowerPC architecture allows

optimizing compilers to schedule instructions to maximize performance through efficient use of the

PowerPC instruction set and register model. The multiple, independent execution units allow compilers to

optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC

architecture can additionally optimize system performance of the PowerPC processors.

Freescale Semiconductor, Inc.

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