ADF4156 datasheet(9/24 Pages) AD

9 / 24 page

ADF4156

Rev. 0 | Page 9 of 24

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 14 is a simplified schematic of

the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the antibacklash pulse, which is

typically 3 ns. This pulse ensures that there is no dead zone in the

PFD transfer function, and gives a consistent reference spur level.

CLR2

DOWN

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 14. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4156 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M4, M3, M2, and M1 (for details,

see Figure 16). Figure 15 shows the MUXOUT section in block

diagram form.

ANALOG LOCK DETECT

MUXOUT

DVDD

THREE-STATE OUTPUT

N DIVIDER OUTPUT

DVDD

DGND

R DIVIDER OUTPUT

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

CLK DIVIDER OUTPUT

R DIVIDER/2

N DIVIDER/2

CONTROL

MUX

Figure 15. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4156 digital section includes a 5-bit RF R counter,

a 12-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 32-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of five latches

on the rising edge of LE. The destination latch is determined by

the state of the three control bits (C3, C2 and C1) in the shift

Figure 2. The truth table for these bits is shown in Table 6.

Figure 16 shows a summary of how the latches are programmed.

PROGRAM MODES

Table 6 and Figure 16 through Figure 20 show how to set up the

program modes in the ADF4156.

A number of settings in the ADF4156 are double buffered.

These include the modulus value, phase value, R counter value,

reference doubler, reference divide-by-2, and current setting.

This means that two events have to occur before the part uses a

new value of any of the double buffered settings. First, the new

value is latched into the device by writing to the appropriate

For example, any time that the modulus value has been

updated, Register R0 must be written to after this, to ensure that

the modulus value is loaded correctly.

Table 6. C3, C2, and C1 Truth Table

Control Bits

ADF4156 Datasheet(PDF) 9 Page - Analog Devices

ADF4156 Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL