ADF4156

Rev. 0 | Page 14 of 24

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

L2

L1

C1

CPI4 CPI3 CPI2 CPI1

0

P1

U2

U1

R5

R4

R3

R2

R1

M12 M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1 C3(0) C2(1) C1(0)

NOISE

MODE

CURRENT

SETTING

5-BIT R COUNTER

CONTROL

BITS

12-BIT MODULUS WORD

C1

CYCLE SLIP

REDUCTION

0DISABLED

1

ENABLED

L1

L2

NOISE MODE

00

LOW NOISE MODE

0

1

RESERVED

1

0

RESERVED

11

LOW SPUR MODE

U1

REFERENCE

DOUBLER

0DISABLED

1

ENABLED

U2

R DIVIDER

0DISABLED

1

ENABLED

P1

PRESCALER

04/5

18/9

CPI4

CPI3

CPI2

CPI1

5.1kΩ

0

0

000.31

0

0

010.63

0

0

100.94

0

0

111.25

0

1

001.57

0

1

011.88

0

1

102.19

0

1

112.5

1

0

002.81

1

0

013.13

1

0

103.44

1

0

113.75

1

1

004.06

1

1

014.38

1

1

104.69

1

1

115.0

M12

M11

..........

M2

M1

INTERPOLATOR MODULUS (MOD)

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

..........

1

1

4095

R5

R4

R3

R2

R1

R COUNTER DIVIDE RATIO

00

0

01

1

00

0

10

2

00

0

11

3

00

1

00

4

..

.

..

..

.

..

..

.

..

11

1

01

29

11

1

1.

30

11

1

11

31

00

0

00

32

Figure 19. MOD/R Register (R2) Map