ADF4156

Rev. 0 | Page 11 of 24

FRAC/INT REGISTER, R0

With R0[2, 1, 0] set to [0, 0, 0], the on-chip FRAC/INT register

is programmed. Figure 17 shows the input data format for

programming this register.

12-Bit INT Value

These twelve bits control what is loaded as the INT value. This

determines the overall feedback division factor. It is used in

Equation 1 (see the INT, FRAC, MOD, and R Relationship

section).

12-Bit FRAC Value

These twelve bits control what is loaded as the FRAC value into

the fractional interpolator. This is part of what determines the

overall feedback division factor. It is also used in Equation 1.

The FRAC value must be less than the value loaded into the

MOD register.

MUXOUT

The on-chip multiplexer is controlled by DB30, DB29, DB28,

and DB27 on the ADF4156. See Figure 17 for the truth table.

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

M4

M3

M2

M1

N12

N11

N10

N9

RE-

SERVED

MUXOUT CONTROL

12-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

CONTROL

BITS

N8

N7

N6

N5

N4

N3

N2

N1

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C3(0) C2(0) C1(0)

M4

M3

M2

M1

OUTPUT

0

0

0

0

THREE-STATE OUTPUT

00

0

1

0

0

1

0

DGND

0

0

1

1

R DIVIDER OUTPUT

0

1

0

0

N DIVIDER OUTPUT

0

1

0

1

ANALOG LOCK DETECT

0

1

1

0

DIGITAL LOCK DETECT

0

1

1

1

SERIAL DATA OUTPUT

1

0

0

0

RESERVED

1

0

0

1

RESERVED

1

0

1

0

CLK DIVIDER

1

0

1

1

RESERVED

1

1

0

0

RESERVED

1

1

0

1

R DIVIDER/2

1

1

1

0

N DIVIDER/2

1

1

1

1

RESERVED

F12

F11

.......... F2

F1

FRACTIONAL VALUE (FRAC)

0

0

.......... 0

0

0

0

0

.......... 0

1

1

0

0

.......... 1

0

2

0

0

.......... 1

1

3

.

.

.......... .

.

.

.

.

.......... .

.

.

.

.

.......... .

.

.

1

1

.......... 0

0

4092

1

1

.......... 0

1

4093

1

1

.......... 1

0

4094

1

1

.........

1

1

4095

N12

N11

N10

N9

N8

N7

N6

N5

N4N3

N2N1INTEGER VALUE (INT)

0

0

0

00

0

0

10

1

1

1

23

0

0

0

00

0

0

11

0

0

0

24

0

0

0

00

0

0

11

0

0

1

25

0

0

0

00

0

0

11

0

1

0

26

.

.

.

..

.

.

..

.

.

.

.

.

.

.

..

.

.

..

.

.

.

.

.

.

.

..

.

.

..

.

.

.

.

1

1

1

11

1

1

11

1

0

1

4093

1

1

1

11

1

1

11

1

1

0

4094

1

1

1

11

1

1

11

1

1

1

4095

Figure 17. FRAC/INT Register (R0) Map