ADF4156

Rev. 0 | Page 12 of 24

PHASE REGISTER, R1

With R1[2, 1, 0] set to [0, 0, 1], the on chip PHASE register is

programmed. Figure 18 shows the input data format for

programming this register.

12-Bit PHASE Value

These twelve bits control what is loaded as the PHASE word.

The word must be less than the MOD value programmed in the

MOD/R register (R2). The word is used to program the RF

See the PHASE RESYNC section for more information. In most

applications, the phase relationship between the RF signal and

the reference is not important. In such applications, the PHASE

value can be used to optimize the fractional and subfractional

spur levels. See the section, Spur Consistency and Fractional

Spur Optimization, for more information.

If neither the PHASE resync nor the spurious optimization

functions are being used, it is recommended that the PHASE

word be set to 1.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

000

0

0

0

0

RESERVED

12-BIT PHASE VALUE (PHASE)

CONTROL

BITS

0

0

0

0

0

0

0

0

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

C3(0) C2(0) C1(1)

P12

P11

..........

P2

P1

PHASE VALUE (PHASE)

0

0

..........

0

0

0

0

0

..........

0

1

1 (RECOMMENDED)

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

..........

1

1

4095

Figure 18. PHASE Register (R1) Map