ADF4156BCPZ datasheet(20/24 Pages) AD

20 / 24 page

ADF4156

Rev. 0 | Page 20 of 24

INTERFACING

The ADF4156 has a simple SPI®-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When latch enable (LE) is high, the 29 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 6 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the lead frame chip scale package (CP-20-1) are

rectangular. The printed circuit board pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider

than the package land width. The land should be centered on

the pad. This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm, and the via barrel should be plated with 1 ounce of

copper to plug the via. The user should connect the printed

circuit board thermal pad to AGND.

ADF4156BCPZ Datasheet(PDF) 20 Page - Analog Devices