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AD9252 Datasheet(PDF) 19 Page - Analog Devices |
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AD9252 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 52 page  AD9252 Rev. 0 | Page 19 of 52 CLOCK INPUT CONSIDERATIONS In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 43). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 40 shows one preferred method for clocking the AD9252. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9252 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9252 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. CLOCK INPUT 0.1µF 0.1µF 0.1µF 39kΩ CMOS DRIVER 50Ω1 OPTIONAL 100Ω 0.1µF CLK CLK 150Ω RESISTOR IS OPTIONAL. CLK– CLK+ ADC AD9252 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF 0.1µF 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812 CLOCK INPUT 50Ω 100Ω CLK– CLK+ ADC AD9252 MINI-CIRCUITS ADT1–1WT, 1:1Z XFMR Figure 43. Single-Ended 1.8 V CMOS Sample Clock CLOCK INPUT 0.1µF 0.1µF 0.1µF CMOS DRIVER 50Ω1 OPTIONAL 100Ω CLK CLK 150Ω RESISTOR IS OPTIONAL. 0.1µF CLK– CLK+ ADC AD9252 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 Figure 40. Transformer-Coupled Differential Clock If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 41. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515 family of clock drivers offers excellent jitter performance. Figure 44. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations CLOCK INPUT 100Ω 0.1µF 0.1µF 0.1µF 0.1µF 240Ω 240Ω CLOCK INPUT AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 50Ω1 50Ω1 CLK CLK 150Ω RESISTORS ARE OPTIONAL. CLK– CLK+ ADC AD9252 PECL DRIVER Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9252 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9252. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. Figure 41. Differential PECL Sample Clock CLOCK INPUT 100Ω 0.1µF 0.1µF 0.1µF 0.1µF 50Ω1 CLOCK INPUT LVDS DRIVER 50Ω1 CLK CLK 150Ω RESISTORS ARE OPTIONAL. CLK– CLK+ ADC AD9252 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Figure 42. Differential LVDS Sample Clock |
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