AD9252 datasheet(21/52 Pages) AD

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AD9252

Rev. 0 | Page 21 of 52

By asserting the PDWN pin high, the AD9252 is placed in

power-down mode. In this state, the ADC typically dissipates

11 mW. During power-down, the LVDS output drivers are placed

in a high impedance state. The AD9252 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length is no longer than 24 inches and that the

differential output traces are kept close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position can be found in Figure 47.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 μF and 4.7 μF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

375 μs to restore full operation.

CH1 500mV/DIV = FCO

CH2 500mV/DIV = DCO

CH3 500mV/DIV = DATA

5.0ns/DIV

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered

when fast wake-up times (~600 ns) are required. See the

Memory Map section for more details on using these features.

Figure 47. LVDS Output Timing Example in ANSI Mode (Default)

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths less than 24 inches on regular FR-4 material is

shown in Figure 48. Figure 49 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is up to

the user to determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches. Additional

SPI options allow the user to further increase the internal ter-

mination (increasing the current) of all eight outputs in order to

drive longer trace lengths (see Figure 50). Even though this

produces sharper rise and fall times on the data edges and is less

prone to bit errors, the power dissipation of the DRVDD supply

increases when this option is used. Also notice in Figure 50 that

the histogram has improved.

Digital Outputs and Timing

The AD9252 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option similar to the IEEE 1596.3 standard using the

SDIO/ODM pin or via the SPI. This LVDS standard can further

reduce the overall power dissipation of the device by approximately

36 mW. See the SDIO/ODM Pin section or Table 15 in the

Memory Map section for more information. The LVDS driver

current is derived on-chip and sets the output current at each

output equal to a nominal 3.5 mA. A 100 Ω differential termination

resistor placed at the LVDS receiver inputs results in a nominal

350 mV swing at the receiver.

The AD9252 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

In cases that require increased driver strength to the DCO and

FCO outputs because of load mismatch, Register 15 allows the

user to increase the drive strength by 2×. To do this, set the

appropriate bit in Register 5. Note that this feature cannot be

used with Bit 4 and Bit 5 in Register 15. Bit 4 and Bit 5 will take

precedence over this feature. See the Memory Map section for

more details.

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