LT8650SPJVPBF datasheet(14/34 Pages) AD

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LT8650SP

Rev. B

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OPERATION

Foreword

The LT8650SP is a dual monolithic step down regula-

tor. The two channels are the same in terms of current

capability and power switch size. The following sections

describe the operation of channel 1 and common circuits.

They will highlight channel 2 differences and interactions

only when relevant. To simplify the application, both VIN1

and VIN2 are assumed to be connected to the same input

supply. However, note that VIN1 must be greater than 3V

for either channel to operate.

Operation

The LT8650SP is a dual monolithic, constant frequency,

peak current mode step-down DC/DC converter. An oscil-

lator, with frequency set using a resistor on the RT pin,

turns on the internal top power switch at the beginning of

each clock cycle. Current in the inductor then increases

until the top switch current comparator trips and turns

off the top power switch. The peak inductor current at

which the top switch turns off is controlled by the voltage

on the VC node. The error amplifier servos the VC node

by comparing the voltage on the VFB pin with an internal

0.8V reference. When the load current increases it causes

areductioninthefeedbackvoltagerelativetothereference

leading the error amplifier to raise the VC voltage until the

average inductor current matches the new load current.

When the top power switch turns off, the synchronous

power switch turns on until the next clock cycle begins or

inductor current falls to zero when not in forced continu-

ous mode (FCM). If overload conditions result in more

than the bottom NMOS current limit flowing through the

bottom switch, the next clock cycle will be delayed until

switch current returns to a safe level.

The S in LT8650SP refers to the second generation Silent

Switchertechnology.Thistechnologyallowsfastswitching

edges for high efficiency at high switching frequencies,

while simultaneously achieving good EMI performance.

This includes the integration of ceramic capacitors into

the package for VIN1, VIN2, VCC, BST1, and BST2 (C1 to

C5 in the Block Diagram). These caps keep all the fast AC

current loops small, which improves EMI performance.

If either EN/UV pin is low, the corresponding channel is

shut down. If both EN/UV pins are low, the LT8650SP is

fully shut down and draws 1.7µA from the input supply.

When the EN/UV pins are above 0.74V, corresponding

switching regulators will become active. 3.7μA is supplied

by VIN1 to common bias circuits for both channels.

Each channel can independently enter Burst Mode opera-

tion to optimize efficiency at light load. Between bursts,

all circuitry associated with controlling the output switch

is shut down, reducing the channel’s contribution to

input supply current. In a typical application, 6.2μA will

be consumed from input supply when regulating both

channels with no load. Ground the SYNC pin for Burst

Mode operation, float it for forced continuous mode (FCM)

or apply a DC voltage from 2.8V to 4V to use FCM with

spread spectrum modulation (SSM). If a clock is applied

to the SYNC pin both channels will synchronize to the

external clock frequency and operate in FCM. While in

FCM the oscillator operates continuously and rising SW

transitions are aligned to the clock. During light loads,

the inductor current is allowed to go negative to maintain

the programmed switching frequency. Minimum current

limits for both power switches are enforced to prevent

large negative inductor current from flowing back to the

input. SSM dithers the switching frequency from the

programmed value set by the RT pin up to 20% higher

than the programmed value to spread out the switching

energy in the frequency domain. The CLKOUT pin has

no output in Burst Mode, but outputs a square wave 90

degrees phase shifted from channel 1 when in FCM. If a

clock is applied to the SYNC pin, the CLKOUT pin has the

same phase and duty cycle as the external clock.

To improve efficiency across all loads, supply current to

internal circuitry can be sourced from the BIAS pin when

biased at 3.3V or above. Otherwise, the internal circuitry

will draw current exclusively from VIN1. The BIAS pin

should be connected to the lowest VOUT programmed at

3.3V or above.

The VC pin allows the loop compensation of the switch-

ing regulator to be optimized based on the programmed

switching frequency. Internal compensation can be se-

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