The following specifications apply for VA = VD = VR = VC = 3.3V, C

Boldface limits apply for T

Symbol

Parameter

Conditions

Min

Typ

(Note 8)

Max

Units

I

IN_SH

Sample and Hold Mode

Source Followers Off

50

70

µA

Input Leakage Current

CDS Gain = 1x

(-70)

(-40)

OS

Source Followers Off

75

105

µA

CDS Gain = 2x

(-105)

(-75)

OS

Source Followers On

-200

-10

200

nA

CDS Gain = 2x

-16

OS

C

SH

Sample/Hold Mode

CDS Gain = 1x

2.5

pF

Equivalent Input Capacitance

(see Figure 11)

CDS Gain = 2x

4

pF

I

IN_CDS

CDS Mode

Source Followers Off

-300

7

300

nA

Input Leakage Current

OS

(-25)

R

CLPIN

CLPIN Switch Resistance

16

50

Ω

(OS

VCLP Reference Circuit Specifications

VCLP DAC Resolution

4

Bits

VCLP DAC Step Size

0.16

V

V

VCLP

VCLP DAC Voltage Min Output

VCLP Config. Register =

0.14

0.26

0.43

V

0001 0000b

VCLP DAC Voltage Max Output

VCLP Config. Register =

2.38

2.68

2.93

V

0001 1111b

Resistor Ladder Enabled

VCLP Config. Register =

1.54

V

1.73

V

0010 xxxxb

I

SC

VCLP DAC Short Circuit Output

Current

VCLP Config. Register =

30

mA

0001 xxxxb

Black Level Offset DAC Specifications

Resolution

10

Bits

Monotonicity

Guaranteed by characterization

Offset Adjustment Range

CDS Gain = 1x

mV

Referred to AFE Input

Minimum DAC Code =

0x000

-614

Maximum DAC Code =

0x3FF

614

CDS Gain = 2x

mV

Minimum DAC Code =

0x000

-307

Maximum DAC Code =

0x3FF

307

Offset Adjustment Range

Minimum DAC Code =

0x000

-16000

-18200

LSB

Referred to AFE Output

Maximum DAC Code =

0x3FF

16000

18200

DAC LSB Step Size

CDS Gain = 1x

1.2

mV

Referred to AFE Output

(32)

(LSB)

DNL

Differential Non-Linearity

-0.95

3.25

LSB

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