MC68L300EC16/D

15

Figure 9 Bus Arbitration Timing Diagram — Idle Bus Case

Figure 10 Show Cycle Timing Diagram

68300 BUS ARB TIM IDLE

CLKOUT

A0

A5

ADDR[23:0]

DATA[15:0]

A2

A3

A0

A5

BR

AS

BG

BGACK

47A

33

33

47A

37

47A

35

CLKOUT

S0

S41

S42

S0

S1

S2

6

ADDR[23:0]

R/W

AS

8

DS

72

DATA[15:0]

BKPT

71

70

12

9

15

73

18

20

SHOW CYCLE

START OF EXTERNAL CYCLE

74

S43

68300 SHW CYC TIM

NOTE:

Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module

wait-state insertion.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com