24

MC68L300EC16/D

Figure 22 Pulse Accumulator — Event Counting Mode (Leading Edge)

NOTE: 1.

A = PAI signal after the synchronizer

2.

B = “A” after the digital filter

3.

*PHI1 is the same frequency as system clock; however, it does not have the same timing.

4.

The external leading edge causes the pulse accumulator to increment and the PAIF flag to be set.

5.

The counter transition from $FF to $00 causes the PAOVF flag to be set.

$FF

$00

PHI1*

PAEN

EXT PIN (PAI)

A

B

PACNT

PAIF

PAOVF

Freescale Semiconductor, Inc.

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