Electronic Components Datasheet Search
  English  ▼

X  

BQ2022ALPR Datasheet(PDF) 13 Page - Texas Instruments

Click here to check the latest version.
Part # BQ2022ALPR
Description  1K-BIT SERIAL EPROM WITH SDQ INTERFACE
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ2022ALPR Datasheet(HTML) 13 Page - Texas Instruments

Back Button BQ2022ALPR Datasheet HTML 9Page - Texas Instruments BQ2022ALPR Datasheet HTML 10Page - Texas Instruments BQ2022ALPR Datasheet HTML 11Page - Texas Instruments BQ2022ALPR Datasheet HTML 12Page - Texas Instruments BQ2022ALPR Datasheet HTML 13Page - Texas Instruments BQ2022ALPR Datasheet HTML 14Page - Texas Instruments BQ2022ALPR Datasheet HTML 15Page - Texas Instruments BQ2022ALPR Datasheet HTML 16Page - Texas Instruments BQ2022ALPR Datasheet HTML 17Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 20 page
background image
www.ti.com
PROGRAM PROFILE BYTE
Other
Command
Codes
bq2022 Transmits
MasterIssuesReset
N
Y
bq2022A
isin
ResetState
FromROM
Command
Program
ProfileCommand?
99h
55h
SDQ SIGNALING
RESET AND PRESENCE PULSE
VPU
VIH
VIL
tRST
tPPD
tPP
RESET
(SentbyHost)
PresencePulse
(Sentbybq2022A)
tRSTREC
WRITE
bq2022A
SLUS724 – SEPTEMBER 2006
The PROGRAM PROFILE byte is read to determine the WRITE MEMORY programming sequence required by
a specific manufacturer. After issuing a ROM command, the host issues the PROGRAM PROFILE BYTE
command, 99h. Figure 12 shows the the bq2022A responds with 55h. This informs the host that the WRITE
MEMORY programming sequence is the one described in the WRITE MEMORY command section of this data
sheet.
Figure 12. PROGRAM PROFILE Command Flow
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 13 shows the initialization timing, whereas Figure 14 and Figure 15
show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq2022A responds during a
READ.
If the DATA bus is driven low for more than 120
µs, the bq2022A may be reset. Figure 13 shows that if the
DATA bus is driven low for more than 480
µs, the bq2022A resets and indicates that it is ready by responding
with a PRESENCE PULSE.
Figure 13. Reset Timing Diagram
The WRITE bit timing diagram in Figure 14 shows that the host initiates the transmission by issuing the tWSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
13
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com