NXP Semiconductors

NVT2001; NVT2002

Bidirectional voltage level translator for open-drain and push-pull applications

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DUT

EN VREFB

VREFA

1.5 V

200 kΩ

SIGNAL

GENERATOR

5.5 V

0.1 µF

1.5 V swing

50 pF

450 Ω

500 Ω

6.6 V

Figure 11. AC test setup

1 V/div

40 ns/div

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Bn

An

GND

GND

Figure 12. Example of typical AC waveform

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VTT

RL

S1

S2 (open)

CL

from output under test

a. Load circuit

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VIH

VIL

VM

VM

input

output

VOH

VOL

VM

VM

b. Timing diagram; high-impedance scope probe used

S2 = translating down, and same voltage.

CL includes probe and jig capacitance.

All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2 ns; tf ≤ 2

ns.

The outputs are measured one at a time, with one transition per measurement.

Figure 13. Load circuit for outputs

12 Performance curves

tPLH up-translation is typically dominated by the RC time constant, i.e., CL(tot) × RPU = 50 pF × 197 Ω = 9.85 ns,

but the Ron × CL(tot) = 50 pF × 5 Ω = 0.250 ns.

tPHL is typically dominated by the external pull-down driver + Ron, which is typically small compared to the tPLH in

an up-translation case.

Enable/disable times are dominated by the RC time constant on the EN pin since the transistor turn off is on the

order of ns, but the enable RC is on the order of ms.

Fall time is dominated by the external pull-down driver with only a slight Ron addition.

Rise time is dominated by the RPU × CL.

Skew time within the part is virtually non-existent, dominated by the difference in bond wire lengths, which is

typically small compared to the board-level routing differences.

Maximum data rate is dominated by the system capacitance and pull-up resistors.

NVT2001_NVT2002

All information provided in this document is subject to legal disclaimers.

© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 4.4 — 22 May 2023

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