| Electronic Components Datasheet Search |
|
TEA2017ABT/2 Datasheet(PDF) 21 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
TEA2017ABT/2 Datasheet(HTML) 21 Page - NXP Semiconductors |
|
21 / 67 page ![]() NXP Semiconductors TEA2017ABT/2 Digital configurable LLC and DCM/QR PFC controller aaa-026794 FEEDBACK CONTROL A/D SNSFB VSNSFB 12 kΩ VPWRGD+VT 960 mV P Figure 19. Optobias regulation Figure 19 shows that when the optocurrent decreases, the internal voltage across the 12 kΩ resistor drops to below the targeted level of 960 mV (= 80 μA (typical) × 12 kΩ). The TEA2017ABT then slowly increases an additional offset at the power level (ΔP). It continues to increase the additional offset until the optocurrent reaches the target of 80 μA (typical). When the optocurrent increases due to a transient, the additional offset to the power level is decreased. As a result, the output voltage decreases which again decreases the optocurrent. In this way, the optocurrent is continuously regulated to the Ireg(SNSFB) level. The behavior of the internal circuitry connected to the SNSFB pin is the same as the behavior of the traditional circuitry. The fixed voltage at the SNSFB pin and the continuous regulation of the optocurrent level does not influence the regulation level. The advantage, however, is a reduction in no-load input power and an optimization of the transient response. When the system operates in low-power mode at the minimum energy per cycle and at minimum duty cycle, it can no longer reduce the optocurrent level to the Ireg(SNSFB) target (» 80 μA typical). If the output power decreases further and the optocurrent increases to above the level of Istart(burst) (» 100 μA typical), the burst mode is triggered. When the output power drops to below this level again, a new burst cycle is started (see Figure 14 and Figure 15). 8.5 Power factor correction (PFC) regulation To achieve a high power factor (PF) and low total harmonic distortion (THD), the input current of the power supply must follow the mains input voltage. However, as the filter capacitances cause a shift of 90° between the mains input current and its voltage, the input filter disrupts PF and THD. To improve PF and THD, the average PFC current is in accordance with a shifted sine wave (see Figure 20). TEA2017ABT_2 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1.1 — 17 May 2023 21 / 67 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |