TEA2017ABTSLASH2 datasheet(40/67 Pages) NXP

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NXP Semiconductors

TEA2017ABT/2

Digital configurable LLC and DCM/QR PFC controller

The PFC burst mode can also be synchronized to the LLC burst mode. It then follows

the on and off periods of the LLC. However, it ensures that the SNSBOOST reaches its

regulation level.

8.8.2.8 Burst mode: Soft-start/soft-stop time

To minimize audible noise of the PFC, a burst mode soft start and soft stop can be

independently selected. The selectable values are: normal, short, and long. The

additional soft-start and soft-stop can also be disabled.

8.8.3 LLC settings

8.8.3.1 LLC disable

Especially for validation purposes, an option is available to disable the LLC. When the

LLC is disabled, a restart is required.

8.8.3.2 Start-up

Maximum (start-up) frequency

The maximum switching frequency of the LLC is limited to a value, which is defined using

a parameter. This value also defines the maximum switching frequency during start-up.

The maximum frequency can be set to different values ranging from 150 kHz to 800 kHz.

LLC soft-start time

The LLC soft-start time defines the rate at which the converter lowers its switching

frequency. This rate can be selected between 2 and 20 which leads to a start-up time

of approximately between 1 ms and 10 ms. However, it depends on the LLC design. A

higher speed lowers the start-up time. However, it can cause a high charge current and

an overshoot at the output voltage.

Maximum primary current during start-up

At start-up, the LLC starts switching at the maximum frequency and ramps down the

frequency until the ΔVSNSCAP reaches the required level. If during this start-up time

the primary current, which reflects the output current, reaches a predefined level, the

frequency is temporarily not further reduced until the primary current drops to below the

level again. This level is measured via the SNSCURLLC pin. The following values can be

selected: 0.5 V, 0.75 V, 1.0 V, or 1.25 V.

8.8.3.3 LLC switching

ΔVSNSCAP dump level

When the system is in low-power mode, a switching period is followed by a waiting

period. The system ensures that it continues at the same stage as where it stopped. To

reach the maximum efficiency, the end of the last switching cycle can be fine-tuned. For

the ΔVSNSCAP dump level, values between 2.525 V and 2.7 V can be selected in steps of

25 mV.

TEA2017ABT_2

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Product data sheet

Rev. 1.1 — 17 May 2023

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