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IDT7035S/L Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT7035S/L
Description  HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM
PDF  19 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7035S/L Datasheet(HTML) 7 Page - Integrated Device Technology

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6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
7
tRC
R/
W
CE
ADDR
tAA
OE
UB, LB
4088 drw 05
(4)
tACE
(4)
tAOE
(4)
tABE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4,5)
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has
no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last
tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Waveform of Read Cycles(5)
7035X15
Com'l Only
7035X20
Com'l Only
Unit
Symbol
Parameter
Min.Max.Min.Max.
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
ns
tAA
Address Access Time
____
15
____
20
ns
tACE
Chip Enable Access Time(3)
____
15
____
20
ns
tABE
Byte Enable Access Time(3)
____
15
____
20
ns
tAOE
Output Enable Access Time
____
10
____
12
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
ns
tPU
Chip Enable to Power Up Time(2)
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(2)
____
15
____
20
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)(3)
10
____
10
____
ns
tSAA
Semaphore Address Access Time(3)
____
15
____
20
ns
4088 tbl 12



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