ICS507-01

PECL CLOCK SYNTHESIZER

PECL MULTIPLIER

IDT™ / ICS™ PECL CLOCK SYNTHESIZER

2

ICS507-01

REV I 041905

Pin Assignment

* At 3.3V, use this selection to get 155.52 MHz from a

16 MHz input.

For lowest phase noise generation of 155.52 MHz, use

a 19.44 MHz crystal and the 8X selection.

Clock Multiplier Select Table

0 = connect pin directly to ground

1 = connect pin directly to VDD

M = leave unconnected (floating)

Pin Descriptions

12

1

11

2

10

3

9

X1/ICLK

4

VDD

5

VDD

6

NC

7

S1

8

GND

S0

OE

NC

GND

NC

PECL

NC

RES

16

15

14

13

PECL

X2

16 Pin (150 mil) SOIC

S1

S0

Multiplier

0

0

9.72X*

0M

10X

01

12X

M

0

6.25X

MM

8X

M1

5X

10

2X

1M

3X

11

4X

Number

Name

Type

Description

1

XI/ICLK

Input

Crystal Connection. Connect to a fundamental parallel mode crystal, or

clock.

2

VDD

Power

Connect to +3.3 V or 5 V, and to VDD on pin 3.

3

VDD

Power

Connect to VDD on pin 2. Decouple with pin 5.

4

S1

Input

Multiplier select pin 1. Determines output frequency per table above.

5

GND

Power

Connect to ground.

6

GND

Power

Connect to ground.

7

NC

—

No connect. Do not connect this pin to anything.

8

PECL

Output

PECL output. Connect to resistor load as shown on page 1.

9

PECL

Output

Complimentary PECL output. Connect to resistor load as shown on

page 1.

10

RES

Input

Bias resistor input. Connect a resistor between this pin and VDD.

11

NC

—

No connect. Do not connect this pin to anything.

12

NC

—

No connect. Do not connect this pin to anything.

13

OE

Input

Output Enable. Tri-states both outputs when low. Internal pull-up.

14

S0

Input

Multiplier select pin 0. Determines output frequency per table above.

15

NC

—

No connect. Do not connect this pin to anything.

16

X2

Output

Crystal Connection. Connect to crystal, or leave unconnected for clock

input.