ICS601-02

LOW PHASE NOISE CLOCK MULTIPLIER

SYNTHESIZERS

IDT™ LOW PHASE NOISE CLOCK MULTIPLIER

2

ICS601-02

REV G 051310

Pin Assignment

Multiplier Select Table

0 = connect directly to ground

1 = connect directly to VDD

Pin Descriptions

1

2

3

VDD

4

VDDP

5

6

GND

7

8

GND

GND

S3

S1

GND

X2

S2

VDD

16

CLK

VDD

X1/ICLK

S0

OE

15

14

13

12

11

10

9

16-pin SOIC

S3

S2

S1 S0

CLK

00

0

0

Input x4/3

00

01

Input x4

00

1

0

Input x25/4

00

11

Input x3

01

0

0

Input x7.5

01

01

Input x5

01

10

Input x6

01

11

Input x8

10

0

0

Input x8/3

10

01

Input x8

10

1

0

Input x12.5

10

11

Input x6

11

0

0

Input x15

11

0

1

Input x10

11

1

0

Input x12

11

1

1

Input x16

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

CLK

Output

Clock output from VCO. Output frequency equals the input frequency times multiplier.

2

VDDP

Power

Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V.

3

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

4

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

5

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

6

X2

XO

Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.

7

S1

Input

Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.

8

X1/ICLK

XI

Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock.

9

S2

Input

Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.

10

S3

Input

Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.

11

S0

Input

Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.

12

OE

Input

Output Enable. Tri-states the output clock when low. Internal pull-up.

13

GND

Power

Connect to ground.

14

GND

Power

Connect to ground.

15

GND

Power

Connect to ground.

16

GND

Power

Connect to ground.