LP62S1024B datasheet(11/17 Pages) AMICC

Part #	LP62S1024B

Description	128K X 8 BIT LOW VOLTAGE CMOS SRAM

PDF	17 Pages

Scroll/Zoom	100%

Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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11 / 17 page

LP62S1024B-I Series

(August, 2004, Version 1.2)

AMIC Technology, Corp.

AC Test Conditions

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Time

5 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

TTL

5pF

TTL

Figure 1. Output Load

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = -40°C to 85°C)

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR1

2.0

3.6

CE1

≥ VCC - 0.2V

VDR2

VCC for Data Retention

2.0

3.6

CE2

≤ 0.2V,

ICCDR1

Data Retention Current

µA

VCC = 2V,

CE1

≥ VCC - 0.2V,

VIN

≥ 0V

ICCDR2

µA

VCC = 2V,

CE2

≤ 0.2V,

VIN

≥ 0V

tCDR

Chip Disable to Data Retention Time

See Retention Waveform

Operation Recovery Time

LP62S1024B-55LLI/70LLI

ICCDR: max.

µA at TA = 0°C to + 40°C

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