AD7762 datasheet(13/28 Pages) AD

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AD7762

Rev. 0 | Page 13 of 28

THEORY OF OPERATION

The AD7762 employs a Σ-Δ conversion technique to convert

the analog input into an equivalent digital word. The modulator

samples the input waveform and outputs an equivalent digital

word to the digital filter at a rate equal to ICLK.

rate to be chosen from 4× to 32×. The third filter has a fixed

decimation rate of 2×, is user programmable, and has a default

configuration. It is described in detail in the Programmable FIR

Filter section. This filter can be bypassed.

Due to the high oversampling rate, that spreads the

quantization noise from 0 to f

ICLK, the noise energy contained in

the band of interest is reduced (

Table 6 lists some characteristics of the default filter. The group

delay of the filter is defined to be the delay to the center of the

impulse response and is equal to the computation + filter delays.

The delay until valid data is available (the DVALID status bit is

set) is equal to 2× the filter delay + the computation delay.

Figure 22 a). To further reduce

the quantization noise, a high order modulator is employed to

shape the noise spectrum; so that most of the noise energy is

shifted out of the band of interest (Figure 22 b).

QUANTIZATION NOISE

fICLK\2

BAND OF INTEREST

fICLK\2

NOISE SHAPING

BAND OF INTEREST

fICLK\2

BAND OF INTEREST

DIGITAL FILTER CUTOFF FREQUENCY

The digital filtering that follows the modulator removes the

large out-of-band quantization noise (Figure 22 c) while also

reducing the data rate from f

ICLK at the input of the filter to

ICLK/8 or less at the output of the filter, depending on the

decimation rate used.

Digital filtering has certain advantages over analog filtering. It

does not introduce significant noise or distortion and can be

made perfectly linear phase.

The AD7762 employs three FIR filters in series. By using

different combinations of decimation ratios and filter selection

and bypassing, data can be obtained from the AD7762 at a large

range of data rates. The first filter receives data from the

modulator at ICLK MHz where it is decimated by four to

output data at ICLK/4 MHz. This partially filtered data can also

be output at this stage. The second filter allows the decimation

Figure 22. Σ-Δ ADC

Table 6. Configuration with Default Filter

ICLK

Frequency

Computation

Delay

Filter 1

Filter 2

Filter 3

Data State

Filter Delay

Pass-Band

Bandwidth

Output Data

Rate (ODR)

20 MHz

4×

2×

Fully filtered

1.775 μs

44.4 μs

250 kHz

625 kHz

20 MHz

4×

8×

Bypassed

Partially filtered

2.6 μs

10.8 μs

140.625 kHz

625 kHz

20 MHz

4×

8×

2×

Fully filtered

2.25 μs

87.6 μs

125 kHz

312.5 kHz

20 MHz

4×

16×

Bypassed

Partially filtered

4.175 μs

20.4 μs

70.3125 kHz

312.5 kHz

20 MHz

4×

16×

2×

Fully filtered

3.1 μs

174 μs

62.5 kHz

156.25 kHz

20 MHz

4×

32×

Bypassed

Partially filtered

7.325 μs

39.6 μs

35.156 kHz

156.25 kHz

20 MHz

4×

32×

2×

Fully filtered

4.65 μs

346.8 μs

31.25 kHz

78.125 kHz

12.288 MHz

4×

8×

2×

Fully filtered

3.66 μs

142.6 μs

76.8 kHz

192 kHz

12.288 MHz

4×

16×

2×

Fully filtered

5.05 μs

283.2 μs

38.4 kHz

96 kHz

12.288 MHz

4×

32×

Bypassed

Partially filtered

11.92 μs

64.45 μs

21.6 kHz

96 kHz

12.288 MHz

4×

32×

2×

Fully filtered

7.57 μs

564.5 μs

19.2 kHz

48 kHz

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