AND8009 datasheet(2/67 Pages) ONSEMI

2 / 67 page

AND8009/D

http://onsemi.com

There are four terminals on all transistor models: Emitter,

Base, Collector, and Substrate (biased to VEE). It should be

noted that circuits can be used single ended by replacing INB

with VBB. Table 1 describes the nomenclature used in the

schematics and netlists.

To simulate a different operating modes all levels, except

VCS, are adjusted with respect to VCC. The VCS is adjusted

with respect to VEE (

[VEE + 1.1 V $ 50 mV)

Table 1. Schematics and Netlist Nomenclature

Parameter

Function Description

VCC

3.3 V FOR LVPECL OR (0 V) FOR LVECL

VCCO

1.6 V − 2.0 V HSTL Output Positive Supply

VCS

Internal Reference Voltage (

[VEE + 1.1 V

$ 50 mV)

VHSTL

HSTL Internal Constant Voltage Source

VEE

−3.3 V FOR LVECL OR (0 V) FOR LVPECL

GND

0 V

VTT

VCC − 2 V TERMINATION PLANE

TRUE INPUT TO CKT

INB or IN

INVERTED INPUT TO CKT

TRUE OUTPUT OF CKT

QB or Q

INVERTED OUTPUT OF CKT

Input Buffer

The Typical Input Buffer schematic (see Table 2) and

netlist are representing structure currently in use on the

existing devices in this family. The schematics require the

addition of ESD models (Figure 15) and package models

(see Table 3) to more accurate model behavior. The internal

input pulldown resistor is shown in the ESD network,

Figure 15. Some devices may also display an internal pullup

resistor to VCC. Refer to specific device data sheet pinout

and logic diagram. It is unnecessary to include an ESD or

package model for the VBB pins of the models because VBB

is intended as an internal node for most applications. If VBB

is modeled as an external node it is usually bypassed because

it is a constant voltage, and adding ESD and Package

parameters provide no additional benefit.

Output Buffer

The output buffer schematics (see Table 2) and netlists

may contain the temperature compensation structure, so

only the ESD and package models need to be added. Any

input or output that is driving or being driven by an off chip

signal should include the ESD and package models. The

output buffers show differential inputs and outputs. When

simulating a single ended output, the termination or load

resistor, package model, ESD structure and output emitter

follower, of the unused output, should not be eliminated to

simplify the system model. The output buffer listing can be

seen in Table 2.

Table 2. Buffer Model Figures

Buffer Model

Figure Number

Page Number

TYPICAL INBUF

OBUF01

OBUF02

OBUF03

OBUF04

OBUF05

OBUF06

OBUF07

OBUF08

OBUF09

OBUF10

OBUF11

Package

A case model for various package types is included to

improve the accuracy of the system model (see Table 3). The

.package model represents the parasitics as they are

measured on a pin. The package pin model should be placed

on each device input pin connecting to an input model, all

device output pins connecting to an output model, VCC, and

VEE. A model can be used at the VEE pin: but is not necessary

since the current in the VEE pin is a constant. Explanations

of the Package Model modes can be found in Appendix A.

Table 3. Available Packages

Package Model

Page Number

8−Lead SO

8−Lead TSSOP

20−Lead SO

20−Lead TSSOP

24−Lead QFN

32−Lead TQFP

52−Lead LQFP

64−Lead LQFP

EP16 Buffer Model

The EP16 interconnect has been completely modeled to

provide a working schematic and output waveforms as

examples of the ECLinPS Plus line. The typical input buffer

may be driven with the output buffer, OBUF01. (See Figure

17, simplified EP16 SPICE model and Figure 18 typical

output waveform.)

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