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AT9933 Datasheet(PDF) 6 Page - Supertex, Inc |
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AT9933 Datasheet(HTML) 6 Page - Supertex, Inc |
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6 / 9 page ![]() 6 AT9933 In this case V DD UVLO cannot be relied upon to turn off the IC at low input voltages when input current levels can get too large. The input current limit must then be designed to limit the input current to safe levels during input undervoltage conditions. Reference An internally trimmed voltage reference of 1.25V is provided at the REF pin. The reference can supply a maximum output current of 500μA to drive external resistor dividers. This reference can be used to set the current thresholds of the two comparators as shown in the Typical Application Cir- cuit. Current Comparators The AT9933 features two identical comparators with a built- in 100mV hysteresis. When the GATE is low, the inverting terminal is connected to 100mV and when the GATE is high, it is connected to GND. One comparator is used for the input current control and the other for the output current control. The input side hysteretic controller is in operation during start-up, overload and input undervoltage conditions. This ensures that the input current never exceeds the designed value. During normal operation, the input current will be less than the programmed current and hence, the output of the input side comparator will be HIGH. The output of the AND gate will then be dictated by the output current controller. The output side hysteretic comparator will be in operation during the steady state operation of the circuit. This com- parator turns the MOSFET on and off based on the LED current. PWM Dimming PWM Dimming can be achieved by applying a TTL-compat- ible square wave signal at the PWM pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or con- nected to GND, the gate driver is disabled and the external MOSFET turns off. The IC is designed so that the signal at the PWMD pin inhibits the driver only and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The recommended PWM Dimming frequency range is from 100Hz to a few kilo hertz. The flying capacitor in the Ćuk converter (C1) is initially charged to the input Voltage VDC (through diodes D1 and D2). When the circuit is turned on and reaches steady state, the voltage across C1 will be VDC+VO. In the absence of diode D2, when the circuit is turned off, capacitor C1 will discharge through the LEDs and the input voltage source VDC. Thus, during PWM dimming, if capacitor C1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. By adding diode D2, the volt- age across capacitor C1 is held at VDC+VO even when the circuit is turned off enabling the circuit to return quickly to its steady state (and bypassing the start-up stage) upon being enabled. Application Information Over-voltage Protection Over-voltage protection can be added by splitting the output side resistor R S2 into two components and adding a zener diode D3 (see the Design Example Circuit on the following page). When there is an open LED condition, the diode D3 will clamp the output voltage and the zener diode current will be regulated by the sum of R S2A and RCS2. Damping Circuit The Ćuk converter is inherently unstable when the output current is being controlled. An uncontrolled input current will lead to an un-damped oscillation between L1 and C1 caus- ing excessively high voltages across C1. To prevent these oscillations, a damping circuit consisting of RD and CD is applied across the capacitor C1. This damping circuit will stabilize the circuit and help in the proper operation of the AT9933 based Ćuk converter. Design and Operation of the Boost-Buck Con- verter For details on the design for a Boost-Buck converter using the AT9933 and the calculation of the damping components, please refer to Application Note AN-H51. |
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