S71GS256 datasheet(91/195 Pages) SPANSION

91 / 195 page

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBitTM Flash Family

Ad vance

Info rmat i o n

Test Conditions

Note: If VIO < VCC, the reference level is 0.5 VIO.

Key to Switching Waveforms

Table 14. Test Specifications

2.7 kΩ

6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent.

Figure 9. Test Setup

Test Condition

All Speeds

Unit

Output Load

1 TTL gate

Output Load Capacitance, CL

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

0.0–VIO

Input timing measurement

reference levels (See Note)

0.5VIO

Output timing measurement

reference levels

0.5 VIO

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z)

0.0 V

0.5 V

0.5 VIO V

Output

Measurement Level

Input

Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

Figure 10. Input Waveforms and Measurement Levels

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