BT481 datasheet(9/52 Pages) ETC

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FUNCTIONAL DESCRIPTION

Pin Information and Block Diagram

L481A_C

Bt481A

110 MHz 256-Word Clor Palette 15-, 16-, and 24-Bit True Color Power-Down RAMDAC

17–19

RS[2:0]

ation being performed, as detailed in Tables 2 and 3.

8–15

D[7:0]

Data Bus (TTL compatible). Data is transferred into and out of the device over this 8-bit

bidirectional data bus. D0 is the least signiﬁcant bit.

6*/8

6-Bit/8-Bit Select Input (TTL compatible). This pin speciﬁes whether the MPU is reading

and writing 8 bits (logical one) or 6 bits (logical zero) of color information each cycle. For

8-bit operation, MPU Bit D[7] is the most signiﬁcant bit during read/write cycles. For

6-bit operation, MPU bit D[5] is the most signiﬁcant bit during read/write cycles. (D[7]

and D[6] are ignored during write cycles and are logical zero during read cycles.)

SENSE*

Sense Output (CMOS compatible). SENSE* is a logical zero if one or more of the IOR,

IOG, and IOB outputs have exceeded the internal voltage reference level. SENSE* may

not be stable while SYNC* is toggling. The SENSE* output can drive only one CMOS

load.

TRUECOL*

True-Color Mode Select Input (TTL compatible). This signal is inverted and logically

ORed with bit A[7] in Command Register A. A logical zero will enable the true-color

modes. By programming the proper command register bits, the user can choose either

5:5:5, 5:6:5, 8:8:8, or 8:8:8:OL and determine whether the pixels are input on a single

clock edge or a dual clock edge (see the Command Register section for details). The

TRUECOL* pin should be tied to VAA to disable the hardware selection of the true-color

mode.

4, 21, 22

VAA

Analog Power. All VAA pins must be connected together on the same PCB plane to pre-

vent latchup.

3, 24

GND

Analog Ground. All GND pins must be connected together on the same PCB plane to

prevent latchup.

Table 1. Pin Descriptions

(3 of 3)

Pin Number

Pin Name

Description

Figure 1. Pinout Diagram

Clock

Ol[0]

Ol[1]

Ol[2]

Ol[3]

Sense*

6*/8

Gnd

Vaa

Sync*

Rd*

Iref

Iob

Iog

Ior

Gnd

Setup

Vaa

Truecol*

Rs[2]

Rs[1]

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