BT481 datasheet(13/52 Pages) ETC

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FUNCTIONAL DESCRIPTION

MPU Interface

L481A_C

Bt481A

110 MHz 256-Word Clor Palette 15-, 16-, and 24-Bit True Color Power-Down RAMDAC

15, 16, and 24/32

Bits-per-Pixel Operation

When the 15, 16, or 24/32 bits-per-pixel modes are activated (see Command Reg-

ister A in the Internal Registers section), the inputs accept 16, 24, or 32 bits of pixel

information from the 8-pin pixel port P[7:0]. The 8-bit inputs form a 16- or 24-bit

pixel (B15–0/B23–B0) to directly drive the 8-bit triple video DACs. The color

lookup table and the read mask register are bypassed. Internally, the unused LSBs

of all DACs are forced to zero in 15 or 16 bits-per-pixel modes. The 16- and 24-bit

word (B15–0/B23–B0) is assigned to the DACs according to Table 4.

15, 16, and 24

Bits-per-Pixel

Dual-Edge Clock

In the 15 and 16 bits-per-pixel dual-edge clock mode (see the Command Register

A, bits A[7:4] description in the Internal Registers section), the least signiﬁcant

byte is latched on the rising edge of the pixel clock when BLANK* high is latched.

Also in this mode, the most signiﬁcant byte is latched on the falling edge of the

pixel clock when BLANK* high is latched. Therefore, only one input clock period

is required to load a 16-bit pixel.

In the 32 bits-per-pixel dual-edge clock mode, 32 bits of data, 24 bits of

true-color and 8 bits of palette index are latched on two rising and two falling edg-

es. Therefore, only two input clock cycles are required to load a 32-bit pixel. If pal-

ette indexing is not required, logical zeros can be written for the palette overlay

data, as location zero in the palette RAM cannot be accessed in this mode. Or pal-

ette overlay data can be masked out through the pixel read mask register. If the pal-

ette index data is not a logical zero or masked, the data will address any one of 255

locations in the palette RAM. Palette data has priority over bypass data.

Table 4. Word Assignments to DACs

8:8:8:8

True Color

Format RGB

8:8:8:8

True Color

Format BGR

5:6:5

XGA Format

5:5:5

TARGA

Format

Comments

B15

Ignored

B7–B0

B23–B16

B15–B11

B14–B10

Red DAC

B15–B8

B10–B5

B9–B5

Green DAC

B23–B16

B7–B0

B4–B0

Blue DAC

B31–B24

Palette or

Masked

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