DATA SHEET

Low Skew, 1-to-4,

Differential-to-LVDS Fanout Buffer

ICS8543I

ICS8543BGI REVISION E NOVEMBER 15, 2012

1

©2012 Integrated Device Technology, Inc.

General Description

The ICS8543I is a low skew, high performance 1-to-4 Differen-

tial-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential

Signaling (LVDS) the ICS8543I provides a low power, low noise, so-

lution for distributing clock signals over controlled impedances of

100

. The ICS8543I has two selectable clock inputs. The CLK,

nCLK pair can accept most standard differential input levels. The

PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.

The clock enable is internally synchronized to eliminate runt pulses

on the outputs during asynchronous assertion/deassertion of the

clock enable pin.

Guaranteed output and part-to-part skew characteristics make the

ICS8543I ideal for those applications demanding well defined perfor-

mance and repeatability.

Features

• Four differential LVDS output pairs

• Selectable differential CLK/nCLK or LVPECL clock inputs

• CLK/nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• PCLK/nPCLK pair can accept the following differential input

levels: LVPECL, CML, SSTL

• Maximum output frequency: 650MHz

• Translates any single-ended input signals to LVDS levels with

resistor bias on nCLK input

• Additive phase Jitter, RMS: 0.164ps (typical)

• Output skew: 40ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Propagation delay: 2.6ns (maximum)

• Full 3.3Vsupply mode

• -40°C to 85°C ambient operating temperature

• Available in lead-free packages

Block Diagram

Pin Assignment

ICS8543I

20-Lead TSSOP

6.5mm x 4.4mm x 0.925

mm

package body

G Package

Top View

0

1

D

Q

LE

0

1

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

CLK_EN

CLK

CLK_SEL

OE

Pulldown

Pulldown

nCLK Pullup

Pullup

Pullup

PCLK Pulldown

nPCLK Pullup

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

OE

nPCLK

PCLK

nCLK

CLK

CLK_SEL

CLK_EN

GND

VDD

Q0

nQ0

VDD

Q1

nQ1

Q2

nQ2

GND

Q3

nQ3