VL-FS-MDLS16163-04 REV. B

(MDLS16163-LED01)

FEB/2004

PAGE 11 OF 12

5.3 Timing Diagram of VDD against V0.

Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0.

VDD

0V

0V

V0

95%

50ms(typical)

LOGIC SUPPLY

VOLTAGE

LCD SUPPLY

VOLTAGE

Figure 4: Timing diagram of VDD against V0.