TPS40140RHHT datasheet(13/65 Pages) TI

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TPS40140

DUAL OR 2-PHASE, STACKABLE CONTROLLER

SLUS660A – SEPTEMBER 2005 – REVISED JULY 2006

Table 4-1. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Power good indicators for CH1 output voltage. This open-drain output connects to a voltage via an

PGOOD1

external resistor

Power good indicators for CH2 output voltage. This open-drain output connects to a voltage via an

PGOOD2

external resistor

Power ground reference for the controller lower gate drivers. There should be a high current return path

PGND

from the sources of the lower MOSFETs to this pin.

A 20

µA current flows from this pin. In a single controller design, this pin should be grounded. In a multi

PHSEL

controller configuration, a 39- k

Ω resistor string sets the voltage on this pin determines the proper phasing

for the slaves. See the section on ' CLOCK MASTER, PHSEL AND CLKIO CONFIGURATIONS'

The output of the internal 5-V regulator. A 4.7-

µF ceramic capacitor should be connected from this pin to

VREG

PGND.

Connecting a resistor from this pin to ground sets the oscillator frequency.

Connect to the switched node on converter CH1. It is the return for the CH 1 upper gate driver. There

should be a high current return path from the source of the upper MOSFET to this pin. This pin is also

SW1

used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET

conduction.

Connect to the switched node on converter CH2. It is the return for the CH 2 upper gate driver. There

should be a high current return path from the source of the upper MOSFET to this pin. This pin is also

SW2

used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET

conduction.

This is an input to the non-inverting input of the error amplifier CH1. This pin is normally connected to the

TRK1

soft-start capacitor or to another voltage that is tracked.

This is an input to the non-inverting input of the error amplifier CH2. This pin is normally connected to the

TRK2

soft-start capacitor or to another voltage that is tracked.

A voltage divider from VIN to this pin determines the input voltage that CH1 starts. When the voltage is

UVLO_CE1

between 0.5 V and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH1 soft

start is allowed to begin.

A voltage divider from VIN to this pin determines the input voltage that CH2 starts. When the voltage is

UVLO_CE2

between 0.5 V and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH2 soft

start is allowed to begin.

Power input for the controller 5V regulator and differential amplifier. A 1.0-

µF ceramic capacitor should be

VDD

connected from this pin to ground.

Non-inverting input of the differential amplifier. This pin should be connected to the output of the converter

VOUT

close to the load point. If the differential amplifier is not used, leave this pin open.

VSHARE

The 1.8 V reference output.

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