SC18IS601 datasheet(4/28 Pages) PHILIPS

4 / 28 page

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

4 of 28

NXP Semiconductors

SC18IS600/601

SPI to I2C-bus interface

Pinning information

5.1 Pinning

5.2 Pin description

Fig 3.

SC18IS600 pin conﬁguration for TSSOP16

Fig 4.

SC18IS601 pin conﬁguration for TSSOP16

SC18IS600IPW

GPIO0

IO5

WAKEUP/IO4

RESET

INT

VSS

GPIO3

MISO

VDD

MOSI

SCLK

SDA

GPIO2

SCL

GPIO1

002aab713

SC18IS601IPW

GPIO0

IO5

WAKEUP/IO4

RESET

INT

VSS

CLKIN

MISO

VDD

MOSI

SCLK

SDA

GPIO2

SCL

GPIO1

002aab714

Table 2.

Pin description

Symbol

Type Description

SC18IS600

SC18IS601

GPIO0

I/O

programmable I/O pin

Chip select. When CS is LOW, the SC18IS600/601 is selected.

RESET

Master Reset. When active (LOW), RESET sets internal registers to

the default values, and resets the I2C-bus and SPI hardware. See

Table 3.

VSS

ground supply voltage

MISO

SPI slave data output

MOSI

SPI slave data input

SDA

I/O

I2C-bus serial data input/output

SCL

I2C-bus serial clock output

GPIO1

I/O

programmable I/O pin

GPIO2

I/O

programmable I/O pin

SCLK

SPI clock input

VDD

2.4 V to 3.6 V supply voltage

GPIO3

I/O

programmable I/O pin

CLKIN

external clock input

INT

Interrupt. When active (LOW), INT informs the CPU that the

SC18IS600/601 has an interrupt to be serviced.

INT is reset (deactivated) either when the I2CStat register is read or as

a result of a master reset (RESET). This pin is an open-drain pin.

WAKEUP/IO4

I/O

Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW

by the host to wake-up from low power state. This pin can also be used

as a quasi-bidirectional I/O when not in a power-down state.

IO5

I/O

quasi-bidirectional I/O pin

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