FXPS7115D4 datasheet(25/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

During soft reset, flash contents are reloaded into the mirror registers and during this process the supply error

flag can get set based on device variation, temperature, and so forth. After 1 ms delay, the expected initial

response from the first 5 commands are shown in Table 32.

Command

Response

Command 1 (DEVSTAT READ)

Ignore response 1

Command 2 (DEVSTAT READ)

Ignore response 2

Command 3 (DEVSTAT READ)

Ignore response 3

Command 4 (SOURCEID_0 READ)

Response 4 - 0X6080XXXX[1]

Command 5 (ANY USER COMMAND)

Response 5 - valid response with reset value of

SOURCEID_0

Table 32. Expected initial responses after tPOR_DataValid post soft reset

[1]

Response 4 is 0x6080XXXX after tPOR_DataValid wait time from soft reset. Otherwise only after tPOR_I2C/POR_SPI wait time from soft reset, response 4 would

be 0x6081XXXX due to DEVINIT bit still set to 1.

7.5.5.1 Basic status field

All responses include a status field (ST[1:0]) that includes the general status of the device and transmitted data

as described below. The contents of the status field is a representation of the device status at the rising edge of

SS_B for the previous SPI command.

ST[1:0]

Status

Description

SF[1:0]

Priority

Device in Initialization

Device in initialization (ENDINIT not set)

Normal Mode

Normal mode(ENDINIT set)

Self-test

Self-test(ST_CTRL[3:0] not equal to '0000')

Internal Error Present

Detailed Status Field

Detailed Status

Field

Table 33. Basic status field for responses to register commands

7.5.5.2 Detailed status field

The response to sensor data requests includes a detailed status field (SF[1:0]). The contents of the detailed

status field is a representation of the device status at the rising edge of SS_B for the previous SPI command.

SF[1:0]

Status Sources

DEVSTAT State

CM_ERROR

Temperature error

Bit set in DSP_STAT

Bit set in DEVSTAT2

User OTP memory error (UF2 or UF1)

User R/W memory error (UF2)

NXP OTP Memory error

U_OTP_ERR set in DEVSTAT2

U_RW_ERR set in DEVSTAT2

F_OTP_ERR set in DEVSTAT2

Test Mode active

Supply error

Reset error

TESTMODE bit set in DEVSTAT

Bit set in DEVSTAT1

DEVRES set

MISO error

SPI error

Bit set in DEVSTAT3

N/A

Table 34. Detailed status bit field descriptions

7.5.5.3 SPI error

The following external SPI conditions result in a SPI error:

• SCLK is high when SS_B is asserted.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.2 — 28 June 2023

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