FXPS7115D4 datasheet(37/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

3. Execute a write to the WRITE_OTP_EN register with region 2 selected and the EX_COMMTYPE and

EX_PADDR bits set as shown in Table 50.

Once the WRITE_OTP_EN register write is completed, a CRC is calculated for the data to be written

to the region, the register values are written to OTP and the region is locked from future writes. The

UOTP_WR_INIT bit remains set.

4. Delay 10 ms to allow the device to complete the writes to OTP.

5. Verify that the OTP write successfully completed by reading back all of the OTP registers using register read

commands.

7.7.6 UF_REGION_W, UF_REGION_R - UF region selection registers (address 14h, 15h)

The UF region load register is a user read/write register that contains the control bits for the UF0 and UF1

regions to be accessed. This register is included in the user read/write array error detection. The UF region

active register is a read-only register that contains the status bits for the UF0 and UF1 regions to be accessed.

This register is included in the user read/write array error detection.

The UF_REGION_W register is readable and writable in SPI mode or I2C mode. The UF_REGION_R register is

readable in SPI mode or I2C mode.

Bit

Symbol

REGION_LOAD[3:0]

Factory default

Access

R/W

Table 51. UF_REGION_W - UF region selection register (address 14h) bit allocation

Bit

Symbol

REGION_ACTIVE[3:0]

Factory default

Access

Table 52. UF_REGION_R - UF region selection register (address 15h) bit allocation

The user OTP regions UF0, UF1, and F share a block of 16 registers. Prior to reading the registers via any

communication interface, the user must ensure that the desired OTP registers are loaded into the readable

registers. Below is the necessary procedure to ensure proper reading of the UF0, UF1, and F registers.

1. Write the desired address range to be read to the REGION_LOAD[3:0] bits in the UF_REGION_W register.

REGION_LOAD[3:0]

OTP register addresses loaded into the readable registers

not applicable

0010 through 1001

reserved

Address Range A0h through AFh

Address Range B0h through BFh

Address Range C0h through CFh

Address Range D0h through DFh

Address Range E0h through EFh

Address Range F0h through FFh

Table 53. REGION_LOAD Bit Definitions

FXPS7115D4

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Product data sheet

Rev. 6.2 — 28 June 2023

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