CDCE6214 datasheet(13/55 Pages) TI

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(2)

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

(3)

The maximum tH_SDA could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD_SDA

by a transition time. This maximum must only be met if the device does not stretch the LOW period (tPWL_SCL) of the SCL signal. If the

clock stretches the SCL, the data must be valid by the setup time before it releases the clock.

8.24 Power Supply Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDD_REF

VDD_REF supply current

25 MHz XTAL, DBL ON

IDD_VCO

VCO and PLL current

fVCO=2400 MHz, PSA = PSB = 4 and N-

divider = 48

IDD_OUT

Output Channel Current

IOD=6, LP-HCSL, 100MHz on OUT3 and

OUT4, 25MHz on OUT0

IDD_OUT

Output Channel Current

IOD = 6, LP-HCSL, 100 MHz on OUT1

and OUT2

17.5

IDD_PDN

Power down current

using reset pin / bits

2.8

IDD_TYP

Typical current

4 x 100 MHz LVDS case using crystal

input and doubler, SSC off

IDD_TYP

Typical current

4 x 100 MHz LP-HCSL case using crystal

input and doubler, SSC off

LPSNR

Power supply noise rejection

OUTx = 100 MHz differential, on one of

VDDx injected sine wave at fINJ = 100 kHz

-61

LPSNR

Power supply noise rejection

OUTx = 100 MHz differential, on one of

VDDx injected sine wave at fINJ = 1 MHz

-57

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CDCE6214Q1TM

SNAS852 – JUNE 2023

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