CDCE6214 datasheet(21/55 Pages) TI

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Table 10-2. Zero Delay Operation (continued)

OPERATION(1)

(2)

REFSEL

R2[1:0] -

REFSEL_SW

R24[1:0] -

IP_SECREF_B

UF_SEL(3)

R24[15] -

IP_PRIREF_BU

F_SEL(3)

R0[8] -

ZDM_EN

R0[10] -

ZDM_CLOCKS

DESCRIPTION

Normal

Operation,

Differential

Input

0h or 1h or 2h

2h or 3h

SECREF/

Differential

Input

Normal

Operation,

Differential

Input

0h or 1h or 3h

PRIREF/

Differential

Input

Normal

Operation,

LVCMOS Input

0h or 1h or 2h

SECREF/

LVCMOS Input

Normal

Operation,

LVCMOS Input

0h or 1h or 3h

PRIREF/

LVCMOS Input

External Zero

Delay Mode,

Differential

Input

0h or 1h or 3h

2h or 3h

Input Clock on

PRIREF,

Feedback clock

on SECREF

External Zero

Delay Mode,

LVCMOS Input

0h or 1h or 3h

Input Clock on

PRIREF,

Feedback clock

on SECREF

Internal Zero

Delay Mode,

Differential

Input

0h or 1h or 3h

Input clock on

PRIREF

Internal Zero

Delay Mode,

Differential

Input

0h or 1h or 3h

Input clock in

PRIREF

(1)

In Zero Delay Mode, all dividers should be programmed such that PLL can lock. On power-up in Zero Delay Mode, PLL would lock

automatically

(2)

For internal Zero Delay Mode, channel 2 is required. Channel 2 should not be powered down

(3)

"X" allows any possible bit field value. It has no impact on the functionality

Figure 10-2. Input/Output Alignment in External Zero Delay Mode for LVCMOS Output

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CDCE6214Q1TM

SNAS852 – JUNE 2023

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