CS5165A datasheet(14/18 Pages) ONSEMI

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CS5165A

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Figure 27. Normal Operation Showing the Guaranteed

Non−Overlap Time Between the High and Low−Side

MOSFET Gate Drives, ILOAD = 14 A

Trace 1 = GATE(H) (5.0 V/div.)

Trace 2 = GATE(L) (5.0 V/div.)

@ 2.2 V

The CS5165A provides adaptive control of the external

NFET conduction times by guaranteeing a typical 65 ns

non−overlap between the upper and lower MOSFET gate drive

pulses. This feature eliminates the potentially catastrophic

effect of “shoot−through current”, a condition during which

both FETs conduct causing them to overheat, self−destruct, and

possibly inflict irreversible damage to the processor.

The most important aspect of FET performance is RDSON,

which effects regulator efficiency and FET thermal

management requirements.

The power dissipated by the MOSFETs may be estimated as

follows:

Switching MOSFET:

Power

+ ILOAD2

RDSON

duty cycle

Synchronous MOSFET:

Power

+ ILOAD2

RDSON

* duty cycle)

Duty Cycle =

VOUT ) (ILOAD

RDSON OF SYNCH FET)

VIN)(ILOAD

RDSON OF SYNCH FET)

* (ILOAD

RDSON OF SWITCH FET)

Off Time Capacitor (COFF)

The COFF timing capacitor sets the regulator off time:

TOFF + COFF

4848.5

The preceding equations for duty cycle can also be used

to calculate the regulator switching frequency and select the

COFF timing capacitor:

COFF +

Perioid

* duty cycle)

4848.5

where:

Period

switching frequency

Schottky Diode for Synchronous FET

For synchronous operation, a Schottky diode may be placed

in parallel with the synchronous FET to conduct the inductor

current upon turn off of the switching FET to improve

efficiency. The CS5165A reference circuit does not use this

device due to it’s excellent design. Instead, the body diode of

the synchronous FET is utilized to reduce cost and conducts the

inductor current. For a design operating at 200 kHz or so, the

low non−overlap time combined with Schottky forward

recovery time may make the benefits of this device not worth

the additional expense. The power dissipation in the

synchronous MOSFET due to body diode conduction can be

estimated by the following equation:

Power

+ VBD

ILOAD

conduction time

switching frequency

Where VBD = the forward drop of the MOSFET body

diode. For the CS5165A demonstration board:

Power

+ 1.6 V

14.2 A

100 ns

200 kHz

+ 0.45 W

This is only 1.1% of the 40 W being delivered to the load.

“Droop” Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to help keep the output

voltage within specification during load transients. To

implement adaptive voltage positioning a “Droop Resistor”

must be connected between the output inductor and output

capacitors and load. This resistor carries the full load current

and should be chosen so that both DC and AC tolerance limits

are met. An embedded PC trace resistor has the distinct

advantage of near zero cost implementation. However, this

droop resistor can vary due to three reasons: 1) the sheet

resistivity variation causes the thickness of the PCB layer to

vary. 2) the mismatch of L/W, and 3) temperature variation.

1. Sheet Resistivity for one ounce copper, the thickness

variation typically 1.15 mil to 1.35 mil. Therefore the

error due to sheet resistivity is:

1.35

* 1.15

1.25

+ 16%

2. Mismatch due to L/W. The variation in L/W is

governed by variations due to the PCB manufacturing

process that affect the geometry and the power

dissipation capability of the droop resistor. The error

due to L/W mismatch is typically 1.0%.

3. Thermal Considerations. Due to I2

× R power losses

the surface temperature of the droop resistor will

increase causing the resistance to increase. Also, the

ambient temperature variation will contribute to the

increase of the resistance, according to the formula:

+ R20[1 ) a20(T * 20)]

where:

R20 = resistance at 20°C

a + 0.00393

°C

T = operating temperature

R = desired droop resistor value

For temperature T = 50

°C, the % R change = 12%

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