CS5165A

http://onsemi.com

17

1. Rapid changes in voltage across parasitic capacitors

and abrupt changes in current in parasitic inductors

are major concerns for a good layout.

2. Keep high currents out of logic grounds.

3. Avoid ground loops as they pick up noise. Use star or

single point grounding. The source of the lower

(synchronous FET) is an ideal point where the input

and output GND planes can be connected.

4. For double−sided PCBs a single large ground plane is

not recommended, since there is little control of

where currents flow and the large surface area can act

as an antenna.

5. Even though double sided PCBs are usually sufficient

for a good layout, four−layer PCBs are the optimum

approach to reducing susceptibility to noise. Use the

two internal layers as the +5.0 V and GND planes, and

the top and bottom layers for the vias.

6. Keep the inductor switching node small by placing

the output inductor, switching and synchronous FETs

close together.

7. The FET gate traces to the IC must be as short,

straight, and wide as possible. Ideally, the IC has to be

placed right next to the FETs.

8. Use fewer, but larger output capacitors, keep the

capacitors clustered, and use multiple layer traces

with heavy copper to keep the parasitic resistance

low.

9. Place the switching FET as close to the +5.0 V input

capacitors as possible.

10. Place the output capacitors as close to the load as

possible.

(pin 16) right at the pin.

(pin 16).

13. The “Droop” Resistor (embedded PCB trace) has to

be wide enough to carry the full load current.

+

COMP

ENABLE

PWRGD

PGND

SS

CS5165A

6.0 m

W

330 pF

LGND

1200

mF/10 V × 3

1.2

mH

Si4410DY

1.0

mF

3.3 k

0.1

mF

1000 pF

5.0 V

MBRS120

1200

mF/10 V × 5

Figure 28. Additional Application Diagram, +5.0 V to +2.8 V @ 14.2 A for 300 MHz Pentium II

PENTIUM II

SYSTEM

Droop Resistor

(Embedded PCB trace)

0.1

mF

Si9410DY

MBRS120

MBRS120

1.0

mF

ENABLE

PWRGD