MC68340 datasheet(242/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 105

5.7.3.6

IMMEDIATE

ARITHMETIC/LOGIC

INSTRUCTIONS.

The immediate

arithmetic/logic instruction table indicates the number of clock periods needed for the

processor to fetch the source immediate data value and to perform the specified

arithmetic/logic instruction using the specified addressing mode. Footnotes indicate when

to account for the appropriate fetch effective or fetch immediate EA times. The total

number of clock cycles is outside the parentheses. The numbers inside parentheses

(r/p/w) are included in the total clock cycle number. All timing data assumes two-clock

reads and writes.

Instruction

Head

Tail

Cycles

MOVEQ

#, Dn

2(0/1/0)

ADDQ

#, Rn

2(0/1/0)

ADDQ

〈FEA〉

5(0/1/x)

SUBQ

#, Rn

2(0/1/0)

SUBQ

〈FEA〉

5(0/1/x)

ADDI

#, Rn

2(0/1/0)

∗

ADDI

〈FEA〉

5(0/1/x)

∗

ANDI

#, Rn

2(0/1/0)

∗

ANDI

〈FEA〉

5(0/1/x)

∗

EORI

#, Rn

2(0/1/0)

∗

EORI

〈FEA〉

5(0/1/x)

∗

ORI

#, Rn

2(0/1/0)

∗

ORI

〈FEA〉

5(0/1/x)

∗

SUBI

#, Rn

2(0/1/0)

∗

SUBI

〈FEA〉

5(0/1/x)

∗

CMPI

#, Rn

2(0/1/0)

∗

CMPI

〈FEA〉

5(0/1/x)

∗

X =

There is one bus cycle for byte and word operands and two bus cycles for long-

word operands. For long-word bus cycles, add two clocks to the tail and to the

number of cycles.

∗= An # fetch EA time must be added for this instruction: 〈FEA〉 +〈FEA〉 + 〈OPER〉

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