AD5370BSTZ datasheet(18/24 Pages) AD

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Preliminary Technical Data

AD5370

Rev. P

rF | Page 18 of 24

SERIAL INTERFACE

The AD5370 contains a high-speed SPI serial interface

operating at clock frequencies up to 50MHz (20MHz for read

operations) To minimize both the power consumption of the

device and on-chip digital noise, the interface powers up fully

only when the device is being written to, that is, on the falling

edge of SYNC.

The serial interface is 2.5 V LVTTL compatible when operating

from a 2.7 V to 3.6 V DVCC supply. It is controlled by four pins,

as follows.

SYNC

Frame synchronization input.

SDI

Serial data input pin.

SCLK

Clocks data in and out of the device.

SDO

Serial data output pin for data readback.

SPI WRITE MODE

The AD5370 allows writing of data via the serial interface to

every register directly accessible to the serial interface, which is

all registers except the X2A and X2B registers and the DAC

registers. The X2A and X2B registers are updated when writing

to the X1A, X1B, M and C registers, and the DAC registers are

updated by LDAC.

The serial word (see Table 8) is 24 bits long. 14 of these bits are

data bits, six bits are address bits, and two bits are mode bits

that determine what is done with the data. Two bits are

reserved.

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into the

AD5370 by clock pulses applied to SCLK. The first falling edge

of SYNC starts the write cycle. At least 24 falling clock edges

must be applied to SCLK to clock in 24 bits of data, before

SYNC is taken high again. If SYNC is taken high before the

24th falling clock edge, the write operation will be aborted.

If a continuous clock is used, SYNC must be taken high before

the 25th falling clock edge. This inhibits the clock within the

AD5370. If more than 24 falling clock edges are applied before

SYNC is taken high again, the input data will be corrupted. If

an externally gated clock of exactly 24 pulses is used, SYNC may

be taken high any time after the 24th falling clock edge.

The input register addressed is updated on the rising edge of

SYNC. In order for another serial transfer to take place, SYNC

must be taken low again

SPI READBACK MODE

The AD5370 allows data readback via the serial interface from

every register directly accessible to the serial interface, which is

all registers except the DAC data registers. In order to read

back a register, it is first necessary to tell the AD5370 which

word whose first two bits are the special function code 00. The

remaining bits then determine if the operation is a readback,

and the register which is to be read back, or if it is a write to of

the special function registers such as the control register.

After the special function write has been performed, if it is a

readback command then data from the selected register will be

clocked out of the SDO pin during the next SPI operation. The

SDO pin is normally three-state but becomes driven as soon as

a read command has been issued. The pin will remain driven

until the registers data has been clocked out. See Figure 5 for

the read timing diagram. Note that due to the timing

requirements of t5 (25ns) the maximum speed of the SPI

interface during a read operation should not exceed 20MHz.

Table 8. Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

D15

D14

D13

D12

D11

D10

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