AD5624R/AD5644R/AD5664R

Rev. A | Page 23 of 28

LDAC FUNCTION

The AD5624R/AD5644R/AD5664R DACs have double-

buffered interfaces consisting of two banks of registers: input

registers and DAC registers. The input registers are connected

directly to the input shift register and the digital code is

transferred to the relevant input register on completion of a

valid write sequence. The DAC registers contain the digital

code used by the resistor strings.

The double-buffered interface is useful if the user requires

simultaneous updating of all DAC outputs. The user can write

to three of the input registers individually and then write to the

remaining input register, updating all DAC registers simulta-

neously. Command 010 is reserved for this software LDAC.

Access to the DAC registers is controlled by the LDAC

function. The LDAC register contains two modes of operation

for each DAC channel. The DAC channels are selected by

setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and

DB0). Command 110 is reserved for setting up the LDAC

register. When the LDAC bit register is set low, the

corresponding DAC registers are latched and the input

registers can change state without affecting the contents of the

DAC registers. When the LDAC bit register is set high,

however, the DAC registers become transparent and the

contents of the input registers are transferred to them on the

an LDAC hardware pin tied permanently low for the selected

DAC channel, that is, synchronous update mode. See Table 14

for the LDAC register mode of operation. See Table 16 for

contents of the input shift register during the LDAC register

setup command.

This flexibility is useful in applications where the user wants to

update select channels simultaneously, while the rest of the

channels update synchronously.

Table 14. LDAC Register Mode of Operation

Load DAC Register

LDAC Bits

(DB3 to DB0)

LDAC Mode of Operation

0

Normal operation (default), DAC register

update is controlled by write command.

1

The DAC registers are updated after new

data is read in on the falling edge of the

INTERNAL REFERENCE SETUP

The on-chip reference is off at power-up by default. This

reference can be turned on or off by setting a software

programmable bit, DB0 in the control register. Table 15 shows

how the state of the bit corresponds to the mode of operation.

Command 111 is reserved for setting up the internal reference

(see Table 8). Table 16 shows how the state of the bits in the

input shift register corresponds to the mode of operation of the

device during internal reference setup.

Table 15. Reference Set-up Register

Internal Reference

Setup Register (DB0)

Action

0

Reference off (default)

1

Reference on

Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R

DB23 to DB22

(MSB)

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB4

DB3

DB2

DB1

DB0 (LSB)

x

1

1

0

x

x

x

x

DAC D

DAC C

DAC B

DAC A

Don’t care

Command bits

(C2 to C0)

Address bits

(A2 to A0); don’t care

Don’t care

Set bit to 0 or 1 for required mode of

operation on respective channel

Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command

DB23 to DB22

(MSB)

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB1

DB0 (LSB)

x

1

1

1

x

x

x

x

1/0

Don’t care

Command bits (C2 to C0)

Address bits (A2 to A0)

Don’t care

Reference setup register