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AD7328 Datasheet(PDF) 30 Page - Analog Devices |
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AD7328 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 36 page ![]() AD7328 Rev. A | Page 30 of 36 POWER VS. THROUGHPUT RATE 20 0 0 1000 THROUGHPUT RATE (kHz) 18 16 14 12 10 8 6 4 2 100 200 300 400 500 600 700 800 900 20MHz SCLK VARIABLE SCLK VCC =5V VDD/VSS = ±12V TA =25°C INTERNAL REFERENCE The power consumption of the AD7328 varies with throughput rate. The static power consumed by the AD7328 is very low, and significant power savings can be achieved as the throughput rate is reduced. Figure 51 and Figure 52 shows the power vs. throughput rate for the AD7328 at a VCC of 3 V and 5 V, respect- tively. Both plots clearly show that the average power consumed by the AD7328 is greatly reduced as the sample frequency is reduced. This is true whether a fixed SCLK value is used or if it is scaled with the sampling frequency. Figure 51 and Figure 52 show the power consumption when operating in normal mode for a fixed 20 MHz SCLK and a variable SCLK that scales with the sampling frequency. 12 0 0 1100 THROUGHPUT RATE (kSPS) 10 8 6 4 2 100 200 300 400 500 600 700 800 900 1000 VARIABLE SCLK 20MHz SCLK VCC =3V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE Figure 52. Power vs. Throughput Rate with 5 V VCC Figure 51. Power vs. Throughput Rate with 3 V VCC |
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