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AD8333 Datasheet(PDF) 4 Page - Analog Devices |
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AD8333 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 28 page  AD8333 Rev. A | Page 4 of 28 Parameter Conditions Min Typ Max Unit PHASE ROTATION PERFORMANCE One CH is reference, other is stepped Phase Increment 16 phase steps per channel 22.5 Degrees Quadrature Phase Error I1 to Q1 and I2 to Q2, 1σ −2 ±0.1 +2 Degrees I/Q Amplitude Imbalance I1 to Q1 and I2 to Q2, 1σ ±0.05 dB Channel-to-Channel Matching Phase match I1/I2 and Q1/Q2; −40°C < TA < 85°C ±1 Degrees Amplitude match I1/I2 and Q1/Q2; −40°C < TA < 85°C ±0.25 dB LOGIC INTERFACES Logic Level High Pin PHxx, Pin RSET, and Pin ENBL 1.7 5 V Logic Level Low Pin PHxx, Pin RSET, and Pin ENBL 0 1.3 V Bias Current Pin PHxx and Pin ENBL Logic high 10 40 90 μA Logic low −30 −7 +10 μA Pin RSET Logic high 50 120 180 μA Logic low −70 −20 0 μA Input Resistance Pin PHxx and Pin ENBL 60 kΩ Pin RSET 20 kΩ Reset Hold Time Reset is asynchronous; clock disabled when RSET goes HI until 300 ns after RSET goes LO 300 ns Minimum Reset Pulse Width 300 ns Reset Response Time See Figure 35 300 ns Phase Response Time See Figure 38 5 μs Enable Response Time See Figure 34 300 ns POWER SUPPLY Pin VPOS and Pin VNEG Supply Voltage ±4.5 ±5 ±6 V Quiescent Current, All Phase Bits = 0 @25°C Pin VPOS 38 44 51 mA Pin VNEG −24 −20 −16 mA Over Temperature −40°C < TA < 85°C Pin VPOS, all phase bits = 0 40 54 mA Pin VNEG −24 −19 mA Quiescent Power Per channel, all phase bits = 0 170 mW Per channel, any 0 or 1 combination of phase bits 190 mW Disable Current All channels disabled Pin VPOS 1.0 1.25 1.5 mA Pin VNEG −300 −200 −100 μA PSRR Pin VPOS to Ix/Qx outputs (measured @ AD8021 output) −81 dB Pin VNEG to Ix/Qx outputs (measured @ AD8021 output) −75 dB |
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