AD73411 datasheet(9/36 Pages) AD

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AD73411

–9–

ARCHITECTURE OVERVIEW

The AD73411 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The AD73411 assembly language uses an algebraic

syntax for ease of coding and readability. A comprehensive set

of development tools supports program development.

ADC

DAC

SERIAL PORT

SPORT 2

REF

EXTERNAL

ADDRESS

BUS

HOST MODE

SERIAL PORTS

SPORT 0

SHIFTER

MAC

ALU

ARITHMETIC UNITS

MEMORY

PROGRAMMABLE

I/O

AND

FLAGS

BYTE DMA

CONTROLLER

TIMER

ADSP-2100 BASE

ARCHITECTURE

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2

DATA

ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

INTERNAL

DMA

PORT

DAG 1

16K DM

(OPTIONAL

8K)

16K PM

(OPTIONAL

8K)

EXTERNAL

DATA

BUS

FULL MEMORY

MODE

EXTERNAL

DATA

BUS

SPORT 1

ANALOG FRONT END

SECTION

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the AD73411. The pro-

cessor section contains three independent computational units:

the ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units directly process 16-bit data and have provi-

sions to support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division primi-

tives are also supported. The MAC performs single-cycle multiply,

multiply/add and multiply/subtract operations with 40 bits of

accumulation. The shifter performs logical and arithmetic shifts,

normalization, denormalization, and derive exponent operations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efﬁcient delivery of operands to these com-

putational units. The sequencer supports conditional jumps,

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the AD73411 executes looped code

with zero overhead; no explicit jump instructions are required

to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modiﬁed by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

The AD73411 can respond to eleven interrupts. There can be

up to six external interrupts (one edge-sensitive, two level-sensitive,

and three conﬁgurable), and seven internal interrupts generated

by the timer, the serial ports (SPORTs), the Byte DMA port

and the power-down circuitry. There is also a master

RESET

signal. The two serial ports provide a complete synchronous

serial interface with optional companding in hardware and a

wide variety of framed or frameless data transmit and receive

modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

The AD73411 provides up to 13 general-purpose flag pins. The

data input and output pins on SPORT1 can be alternatively

conﬁgured as an input flag and an output flag. In addition, eight

flags are programmable as inputs or outputs and three flags are

always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) is decremented every n pro-

cessor cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Analog Front End

The AFE section is conﬁgured as a separate block that is normally

connected to either SPORT0 or SPORT1 of the DSP section.

As it is not hardwired to either SPORT, users have total flexibil-

ity in how they wish to allocate system resources to support the

AFE. It is also possible to further expand the number of analog

I/O channels connected to the SPORT by cascading other single

or dual channel AFEs (AD73311 or AD73322) external to the

AD73411.

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