AD73411 datasheet(27/36 Pages) AD

27 / 36 page

REV. 0

AD73411

–27–

ACCESSIBLE WHEN

DMOVLAY = 2

ACCESSIBLE WHEN

DMOVLAY = 1

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

INTERNAL

MEMORY

EXTERNAL

MEMORY

0x0000–

0x1FFF

0x0000–

0x1FFF

0x0000–

0x1FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

x3FFF

0x2000

0x1FFF

INTERNAL

8160

WORDS

x0000

DATA MEMORY

ADDRESS

8K INTERNAL

DMOVLAY = 0

EXTERNAL 8K

DMOVLAY = 1, 2

0x3FE0

0x3FDF

Figure 16. Data Memory Map

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0). The DMOVLAY bits are deﬁned in Table XX.

Table XX. DMOVLAY Bits

DMOVLAY

Memory

A13

A12:0

Internal

Not Applicable Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000

and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000

and 0x3FFF

I/O Space (Full Memory Mode)

The AD73411 supports an additional external memory space

called I/O space. This space is designed to support simple connec-

tions to peripherals (such as data converters and external registers)

or to bus interface ASIC data registers. I/O space supports 2048

locations of 16-bit-wide data. The lower 11-bits of the external

address bus are used; the upper three bits are undeﬁned. Two

instructions were added to the core ADSP-2100 Family Instruc-

tion Set to read from and write to I/O memory space. The I/O

space also has four dedicated 3-bit wait state registers, IOWAIT0-

3, that specify up to seven wait states to be automatically generated

for each of four regions. The wait states act on address ranges as

shown in Table XXI.

Table XXI. Wait States

Address Range

Wait State Register

0x000–0x1FF

IOWAIT0

0x200–0x3FF

IOWAIT1

0x400–0x5FF

IOWAIT2

0x600–0x7FF

IOWAIT3

Composite Memory Select (

CMS)

The AD73411 has a programmable memory select signal that is

useful for generating memory select signals for memories mapped

to more than one space. The

CMS signal is generated to have

the same timing as each of the individual memory select signals

(

PMS, DMS, BMS, IOMS) but can combine their functionality.

Each bit in the CMSSEL register, when set, causes the

CMS

signal to be asserted when the selected memory select is asserted.

For example, to use a 32K word memory to act as both program

and data memory, set the

PMS and DMS bits in the CMSSEL

CMS pin to drive the chip select of the

memory; use either

DMS or PMS as the additional address bit.

The

CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the

CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at reset,

except the

BMS bit.

Boot Memory Select (

BMS) Disable

The AD73411 also lets you boot the processor from one exter-

nal memory space while using a different external memory space

for BDMA transfers during normal operation. You can use the

CMS to select the ﬁrst external memory space for BDMA trans-

fers and

BMS to select the second external memory space for

booting. The

BMS signal can be disabled by setting Bit 3 of the

System Control Register to 1. The System Control Register is

illustrated in Figure 17.

SYSTEM CONTROL REGISTER

PWAIT

PROGRAM MEMORY

WAIT STATES

000

15 14 13 12 11 10

43210

DM (0x3FFF)

BMS ENABLE

0 = ENABLED

1 = DISABLED

SPORT0 ENABLE

1 = ENABLED

0 = DISABLED

SPORT1 ENABLE

1 = ENABLED

0 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO,

IRQ0,

IRQ1, SCLK

Figure 17. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The BDMA Control Regis-

ter is shown in Figure 18. The byte memory space consists of

256 pages, each of which is 16K

× 8.

The byte memory space on the AD73411 supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg

× 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally, and steals only one

DSP cycle per 8-, 16-, or 24-bit word transferred.

BDMA CONTROL

BMPAGE

BTYPE

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

000

15 14 13 12 11 10

43210

DM (0x3FE3)

BDIR

0 = LOAD FROM BM

1 = STORE TO BM

Figure 18. BDMA Control Register

The BDMA circuit supports four different data formats that are

selected by the BTYPE register ﬁeld. The appropriate number

of 8-bit accesses are done from the byte memory space to build

the word size selected. Table XXII shows the data formats sup-

ported by the BDMA circuit.

AD73411 Datasheet(PDF) 27 Page - Analog Devices

AD73411 Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL