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PML260SN Datasheet(PDF) 2 Page - NXP Semiconductors |
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PML260SN Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 12 page ![]() PML260SN_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 May 2006 2 of 12 Philips Semiconductors PML260SN N-channel TrenchMOS standard level FET 3. Ordering information 4. Limiting values Table 2. Ordering information Type number Package Name Description Version PML260SN HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3.3 × 3.3 × 0.85 mm SOT873-1 Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ T j ≤ 150 °C - 200 V VGS gate-source voltage - ±20 V ID drain current Tmb =25 °C; VGS = 10 V; see Figure 2 and 3 - 8.8 A Tmb = 100 °C; VGS = 10 V; see Figure 2 - 5.5 A IDM peak drain current Tmb =25 °C; pulsed; tp ≤ 10 µs; see Figure 3 -15 A Ptot total power dissipation Tmb =25 °C; see Figure 1 -50 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source current Tmb =25 °C - 8.8 A ISM peak source current Tmb =25 °C; pulsed; tp ≤ 10 µs - 15 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID = 3.5 A; tp = 0.05 ms; VDS ≤ 200 V; RGS =50 Ω; VGS = 10 V; starting at Tj =25 °C -22 mJ |
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