TAS5261 datasheet(16/21 Pages) TI

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THEORY OF OPERATION

Power Supplies

System Power-Up/Power-Down Sequence

Powering Up

Powering Down

TAS5261

SLES188 – AUGUST 2006

PCB placement, and routing. As indicated, each half

bridge has independent power-stage supply pins

(PVDD_x). For optimal electrical performance, EMI

To facilitate system design, the TAS5261 needs only

compliance, and system reliability, it is important that

12-V

supply

addition

typical

50-V

each PVDD_x pin is decoupled with two 100-nF

power-stage supply. An internal voltage regulator

ceramic capacitors placed as close as possible to

provides suitable voltage levels for the digital and

each supply pin on the same side of the PCB as the

low-voltage analog circuitry. Additionally, all circuitry

TAS5261 location. It is recommended to follow the

requiring a floating voltage supply, e.g., the high-side

PCB layout of the TAS5261 reference design. For

gate drive, is accommodated by built-in bootstrap

additional information on the recommended power

circuitry requiring only a few external capacitors.

supply and required components, see the application

diagrams given in this data sheet.

provide

outstanding

electrical

and

acoustic

characteristics, the PWM signal path, including gate

The

12-V

supply

should

powered

from

drive and output stage, is designed as identical,

low-noise, low-output-impedance voltage regulator.

independent half bridges. For this reason, each half

Likewise, the 50-V power-stage supply is assumed to

bridge has separated gate-drive supply (GVDD_x),

have low output impedance and low noise. The

bootstrap pins (BST_x) and power-stage supply pins

internal

POR

circuit

eliminates

the

need

for

(PVDD_x). Furthermore, an additional pin (VDD) is

power-supply sequencing. Moreover, the TAS5261 is

provided as power supply for all common circuits.

fully protected against erroneous power-stage turn

Although supplied from the same 12-V source, it is

due

parasitic

gate

charging.

Thus,

highly recommended to separate GVDD_x and VDD

voltage-supply ramp rates (dv/dt) are noncritical

on the printed circuit board (PCB) by RC filters (see

within the specified range (see the Recommended

application diagram for details). These RC filters

Operating Conditions section of this data sheet).

provide the recommended high-frequency isolation.

Special attention should be paid to placing all

decoupling capacitors as close to their associated

pins as possible. In general, inductance between the

power-supply pins and decoupling capacitors must

be avoided. (See reference board documentation for

There is no power-up sequence is required for the

additional information.)

TAS5261. The outputs of the H-bridge remain in a

high-impedance state until the gate-drive supply

For a properly functioning bootstrap circuit, a small

voltage (GVDD_x) and VDD voltage are above the

ceramic capacitor must be connected from each

undervoltage protection (UVP) voltage threshold (see

bootstrap pin (BST_x) to the power-stage output pin

the Electrical Characteristics section of this data

(OUT_x). When the power-stage output is low, the

sheet). Although not specifically required, it is

bootstrap capacitor is charged through an internal

recommended to hold RESET in a low state while

diode

connected

between

the

gate-drive

powering up the device. This allows an internal

power-supply pin (GVDD_x) and the bootstrap pin.

circuit to charge the external bootstrap capacitors by

When the power-stage output voltage is high, the

enabling a weak pulldown of the half-bridge output.

bootstrap capacitor voltage is shifted above the

output voltage potential and, thus, provides a

While powering up the TAS5261, RESET should be

suitable voltage supply for the high-side gate driver.

held low.

In an application with PWM switching frequencies in

the range of 352 kHz to 384 kHz, it is recommended

to use 33-nF ceramic capacitors, size 0603 or 0805,

There is no power-down sequence is required for the

for the bootstrap capacitor. These 33-nF capacitors

TAS5261. The device remains fully operational as

ensure

sufficient

energy

storage,

even

during

long as the gate-drive supply (GVDD_x) voltage and

minimal PWM duty cycles, to keep the high-side

VDD voltage are above the undervoltage protection

power-stage FET (LDMOS) fully started during all of

(UVP)

threshold

level

(see

the

Electrical

the remaining part of the PWM cycle. In an

Characteristics section of this data sheet). Although

application running at a reduced switching frequency,

not specifically required, it is a good practice to hold

generally 250 kHz to 192 kHz, the bootstrap

RESET low during power down, thus, preventing

capacitor might need to be increased in value.

audible artifacts including pops and clicks.

Special attention should be paid to the power-stage

power supply – this includes component selection,

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