IR3084 datasheet(41/45 Pages) IRF

41 / 45 page

IR3084

Page 41 of 45

07/20/2005

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

•

Connect the ground tab under the control IC to LGND plane through a via.

•

Place the following critical components on the same layer as control IC and position them as close as

possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RCC/DEL. Avoid using any

via for the connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible

to EAOUT, FB and VDRP pins. Avoid using any via for the connection.

•

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS−, and avoid crossing

over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

•

Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast

transition nodes.

CVCC

REGFB

VOSNS-

ROSC

VDAC

To VIN

ROSC

CVDAC

To SYSTEM

LGND PLANE

LGND

SS/DEL

ENABLE

VRRDY

OCSET

RVDAC

ROCSET

RVCC

CSS/DEL

RREGSET

To Voltage

Remote Sense

VID1

VID0

VSETPT

REGDRV

REGSET

RSETPT

GND

IR3084 Datasheet(PDF) 41 Page - International Rectifier

IR3084 Datasheet(HTML) 41 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL